Commit d109c4bb authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux 

Pull arm64 fixes from Will Deacon:
 "This addresses some problems with filesystem writeback due to the
  recently merged hardware DBM patches, which caused us to treat some
  read-only pages as dirty.

  There are also some other, less significant fixes that are described
  in the summary below:

  A mixture of fixes for regressions introduced during the merge window,
  some longer standing problems that we spotted and a couple of hardware
  errata.  The main changes are:

   - Fix fallout from the h/w DBM patches, causing filesystem writeback
     issues on both v8 and v8.1 CPUs

   - Workaround for Cortex-A53 erratum #843419 in the module loader

   - Fix for long-standing issue with compat big-endian signal handlers
     using the saved floating point state"

* tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux:
  arm64: errata: add module build workaround for erratum #843419
  arm64: compat: fix vfp save/restore across signal handlers in big-endian
  arm64: cpu hotplug: ensure we mask out CPU_TASKS_FROZEN in notifiers
  arm64: head.S: initialise mdcr_el2 in el2_setup
  arm64: enable generic idle loop
  arm64: pgtable: use a single bit for PTE_WRITE regardless of DBM
  arm64: Fix pte_modify() to preserve the hardware dirty information
  arm64: Fix the pte_hw_dirty() check when AF/DBM is enabled
  arm64: dma-mapping: check whether cma area is initialized or not
parents 42dc2a30 df057cc7

arch/arm64/Kconfig

+17 −0
Original line number Diff line number Diff line
@@ -32,6 +32,7 @@ config ARM64 
	select GENERIC_CLOCKEVENTS_BROADCAST

	select GENERIC_CPU_AUTOPROBE

	select GENERIC_EARLY_IOREMAP

	select GENERIC_IDLE_POLL_SETUP

	select GENERIC_IRQ_PROBE

	select GENERIC_IRQ_SHOW

	select GENERIC_IRQ_SHOW_LEVEL
@@ -331,6 +332,22 @@ config ARM64_ERRATUM_845719 


	  If unsure, say Y.



config ARM64_ERRATUM_843419

	bool "Cortex-A53: 843419: A load or store might access an incorrect address"

	depends on MODULES

	default y

	help

	  This option builds kernel modules using the large memory model in

	  order to avoid the use of the ADRP instruction, which can cause

	  a subsequent memory access to use an incorrect address on Cortex-A53

	  parts up to r0p4.



	  Note that the kernel itself must be linked with a version of ld

	  which fixes potentially affected ADRP instructions through the

	  use of veneers.



	  If unsure, say Y.



endmenu

arch/arm64/Makefile

+4 −0
Original line number Diff line number Diff line
@@ -41,6 +41,10 @@ endif 


CHECKFLAGS	+= -D__aarch64__



ifeq ($(CONFIG_ARM64_ERRATUM_843419), y)

CFLAGS_MODULE	+= -mcmodel=large

endif



# Default value

head-y		:= arch/arm64/kernel/head.o

arch/arm64/include/asm/pgtable.h

+4 −8
Original line number Diff line number Diff line
@@ -26,13 +26,9 @@ 
 * Software defined PTE bits definition.

 */

#define PTE_VALID		(_AT(pteval_t, 1) << 0)

#define PTE_WRITE		(PTE_DBM)		 /* same as DBM (51) */

#define PTE_DIRTY		(_AT(pteval_t, 1) << 55)

#define PTE_SPECIAL		(_AT(pteval_t, 1) << 56)

#ifdef CONFIG_ARM64_HW_AFDBM

#define PTE_WRITE		(PTE_DBM)		 /* same as DBM */

#else

#define PTE_WRITE		(_AT(pteval_t, 1) << 57)

#endif

#define PTE_PROT_NONE		(_AT(pteval_t, 1) << 58) /* only when !PTE_VALID */



/*
@@ -146,7 +142,7 @@ extern struct page *empty_zero_page; 
#define pte_exec(pte)		(!(pte_val(pte) & PTE_UXN))



#ifdef CONFIG_ARM64_HW_AFDBM

#define pte_hw_dirty(pte)	(!(pte_val(pte) & PTE_RDONLY))

#define pte_hw_dirty(pte)	(pte_write(pte) && !(pte_val(pte) & PTE_RDONLY))

#else

#define pte_hw_dirty(pte)	(0)

#endif
@@ -238,7 +234,7 @@ extern void __sync_icache_dcache(pte_t pteval, unsigned long addr); 
 * When hardware DBM is not present, the sofware PTE_DIRTY bit is updated via

 * the page fault mechanism. Checking the dirty status of a pte becomes:

 *

 *   PTE_DIRTY || !PTE_RDONLY

 *   PTE_DIRTY || (PTE_WRITE && !PTE_RDONLY)

 */

static inline void set_pte_at(struct mm_struct *mm, unsigned long addr,

			      pte_t *ptep, pte_t pte)
@@ -503,7 +499,7 @@ static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) 
			      PTE_PROT_NONE | PTE_WRITE | PTE_TYPE_MASK;

	/* preserve the hardware dirty information */

	if (pte_hw_dirty(pte))

		newprot |= PTE_DIRTY;

		pte = pte_mkdirty(pte);

	pte_val(pte) = (pte_val(pte) & ~mask) | (pgprot_val(newprot) & mask);

	return pte;

}

arch/arm64/kernel/debug-monitors.c

+1 −1
Original line number Diff line number Diff line
@@ -134,7 +134,7 @@ static int os_lock_notify(struct notifier_block *self, 
				    unsigned long action, void *data)

{

	int cpu = (unsigned long)data;

	if (action == CPU_ONLINE)

	if ((action & ~CPU_TASKS_FROZEN) == CPU_ONLINE)

		smp_call_function_single(cpu, clear_os_lock, NULL, 1);

	return NOTIFY_OK;

}

arch/arm64/kernel/head.S

+5 −0
Original line number Diff line number Diff line
@@ -523,6 +523,11 @@ CPU_LE( movk x0, #0x30d0, lsl #16 ) // Clear EE and E0E on LE systems 
	msr	hstr_el2, xzr			// Disable CP15 traps to EL2

#endif



	/* EL2 debug */

	mrs	x0, pmcr_el0			// Disable debug access traps

	ubfx	x0, x0, #11, #5			// to EL2 and allow access to

	msr	mdcr_el2, x0			// all PMU counters from EL1



	/* Stage-2 translation */

	msr	vttbr_el2, xzr

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