drm/amd/display: change dml init to use default structs

#include "display_mode_lib.h"

#include "dc_features.h"

static const struct _vcs_dpi_ip_params_st dcn1_0_ip = {

	.rob_buffer_size_kbytes = 64,

	.det_buffer_size_kbytes = 164,

	.dpte_buffer_size_in_pte_reqs = 42,

	.dpp_output_buffer_pixels = 2560,

	.opp_output_buffer_lines = 1,

	.pixel_chunk_size_kbytes = 8,

	.pte_enable = 1,

	.pte_chunk_size_kbytes = 2,

	.meta_chunk_size_kbytes = 2,

	.writeback_chunk_size_kbytes = 2,

	.line_buffer_size_bits = 589824,

	.max_line_buffer_lines = 12,

	.IsLineBufferBppFixed = 0,

	.LineBufferFixedBpp = -1,

	.writeback_luma_buffer_size_kbytes = 12,

	.writeback_chroma_buffer_size_kbytes = 8,

	.max_num_dpp = 4,

	.max_num_wb = 2,

	.max_dchub_pscl_bw_pix_per_clk = 4,

	.max_pscl_lb_bw_pix_per_clk = 2,

	.max_lb_vscl_bw_pix_per_clk = 4,

	.max_vscl_hscl_bw_pix_per_clk = 4,

	.max_hscl_ratio = 4,

	.max_vscl_ratio = 4,

	.hscl_mults = 4,

	.vscl_mults = 4,

	.max_hscl_taps = 8,

	.max_vscl_taps = 8,

	.dispclk_ramp_margin_percent = 1,

	.underscan_factor = 1.10,

	.min_vblank_lines = 14,

	.dppclk_delay_subtotal = 90,

	.dispclk_delay_subtotal = 42,

	.dcfclk_cstate_latency = 10,

	.max_inter_dcn_tile_repeaters = 8,

	.can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one = 0,

	.bug_forcing_LC_req_same_size_fixed = 0,

};

static const struct _vcs_dpi_soc_bounding_box_st dcn1_0_soc = {

	.sr_exit_time_us = 9.0,

	.sr_enter_plus_exit_time_us = 11.0,

	.urgent_latency_us = 4.0,

	.writeback_latency_us = 12.0,

	.ideal_dram_bw_after_urgent_percent = 80.0,

	.max_request_size_bytes = 256,

	.downspread_percent = 0.5,

	.dram_page_open_time_ns = 50.0,

	.dram_rw_turnaround_time_ns = 17.5,

	.dram_return_buffer_per_channel_bytes = 8192,

	.round_trip_ping_latency_dcfclk_cycles = 128,

	.urgent_out_of_order_return_per_channel_bytes = 256,

	.channel_interleave_bytes = 256,

	.num_banks = 8,

	.num_chans = 2,

	.vmm_page_size_bytes = 4096,

	.dram_clock_change_latency_us = 17.0,

	.writeback_dram_clock_change_latency_us = 23.0,

	.return_bus_width_bytes = 64,

};

static void set_soc_bounding_box(struct _vcs_dpi_soc_bounding_box_st *soc, enum dml_project project)

{

	if (project == DML_PROJECT_RAVEN1) {

		soc->sr_exit_time_us = 9.0;

		soc->sr_enter_plus_exit_time_us = 11.0;

		soc->urgent_latency_us = 4.0;

		soc->writeback_latency_us = 12.0;

		soc->ideal_dram_bw_after_urgent_percent = 80.0;

		soc->max_request_size_bytes = 256;

		soc->downspread_percent = 0.5;

		soc->dram_page_open_time_ns = 50.0;

		soc->dram_rw_turnaround_time_ns = 17.5;

		soc->dram_return_buffer_per_channel_bytes = 8192;

		soc->round_trip_ping_latency_dcfclk_cycles = 128;

		soc->urgent_out_of_order_return_per_channel_bytes = 256;

		soc->channel_interleave_bytes = 256;

		soc->num_banks = 8;

		soc->num_chans = 2;

		soc->vmm_page_size_bytes = 4096;

		soc->dram_clock_change_latency_us = 17.0;

		soc->writeback_dram_clock_change_latency_us = 23.0;

		soc->return_bus_width_bytes = 64;

	} else {

		BREAK_TO_DEBUGGER(); /* Invalid Project Specified */

	switch (project) {

	case DML_PROJECT_RAVEN1:

		*soc = dcn1_0_soc;

		break;

	default:

		ASSERT(0);

		break;

	}

}

static void set_ip_params(struct _vcs_dpi_ip_params_st *ip, enum dml_project project)

{

	if (project == DML_PROJECT_RAVEN1) {

		ip->rob_buffer_size_kbytes = 64;

		ip->det_buffer_size_kbytes = 164;

		ip->dpte_buffer_size_in_pte_reqs = 42;

		ip->dpp_output_buffer_pixels = 2560;

		ip->opp_output_buffer_lines = 1;

		ip->pixel_chunk_size_kbytes = 8;

		ip->pte_enable = 1;

		ip->pte_chunk_size_kbytes = 2;

		ip->meta_chunk_size_kbytes = 2;

		ip->writeback_chunk_size_kbytes = 2;

		ip->line_buffer_size_bits = 589824;

		ip->max_line_buffer_lines = 12;

		ip->IsLineBufferBppFixed = 0;

		ip->LineBufferFixedBpp = -1;

		ip->writeback_luma_buffer_size_kbytes = 12;

		ip->writeback_chroma_buffer_size_kbytes = 8;

		ip->max_num_dpp = 4;

		ip->max_num_wb = 2;

		ip->max_dchub_pscl_bw_pix_per_clk = 4;

		ip->max_pscl_lb_bw_pix_per_clk = 2;

		ip->max_lb_vscl_bw_pix_per_clk = 4;

		ip->max_vscl_hscl_bw_pix_per_clk = 4;

		ip->max_hscl_ratio = 4;

		ip->max_vscl_ratio = 4;

		ip->hscl_mults = 4;

		ip->vscl_mults = 4;

		ip->max_hscl_taps = 8;

		ip->max_vscl_taps = 8;

		ip->dispclk_ramp_margin_percent = 1;

		ip->underscan_factor = 1.10;

		ip->min_vblank_lines = 14;

		ip->dppclk_delay_subtotal = 90;

		ip->dispclk_delay_subtotal = 42;

		ip->dcfclk_cstate_latency = 10;

		ip->max_inter_dcn_tile_repeaters = 8;

		ip->can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one = 0;

		ip->bug_forcing_LC_req_same_size_fixed = 0;

	} else {

		BREAK_TO_DEBUGGER(); /* Invalid Project Specified */

	switch (project) {

	case DML_PROJECT_RAVEN1:

		*ip = dcn1_0_ip;

		break;

	default:

		ASSERT(0);

		break;

	}

}