Commit d0e22329 authored by Russell King's avatar Russell King
Browse files

ARM: qcom: remove unnecessary boot_lock 



The boot_lock is something that was required for ARM development
platforms to ensure that the delay calibration worked properly.  This
is not necessary for modern platforms that have better bus bandwidth
and do not need to calibrate the delay loop for secondary cores.
Remove the boot_lock entirely.

Signed-off-by: default avatarRussell King <rmk+kernel@armlinux.org.uk>
parent bfeffd15

arch/arm/mach-qcom/platsmp.c

+0 −26
Original line number Diff line number Diff line
@@ -46,8 +46,6 @@ 


extern void secondary_startup_arm(void);



static DEFINE_SPINLOCK(boot_lock);



#ifdef CONFIG_HOTPLUG_CPU

static void qcom_cpu_die(unsigned int cpu)

{
@@ -55,15 +53,6 @@ static void qcom_cpu_die(unsigned int cpu) 
}

#endif



static void qcom_secondary_init(unsigned int cpu)

{

	/*

	 * Synchronise with the boot thread.

	 */

	spin_lock(&boot_lock);

	spin_unlock(&boot_lock);

}



static int scss_release_secondary(unsigned int cpu)

{

	struct device_node *node;
@@ -280,12 +269,6 @@ static int qcom_boot_secondary(unsigned int cpu, int (*func)(unsigned int)) 
			per_cpu(cold_boot_done, cpu) = true;

	}



	/*

	 * set synchronisation state between this boot processor

	 * and the secondary one

	 */

	spin_lock(&boot_lock);



	/*

	 * Send the secondary CPU a soft interrupt, thereby causing

	 * the boot monitor to read the system wide flags register,
@@ -293,12 +276,6 @@ static int qcom_boot_secondary(unsigned int cpu, int (*func)(unsigned int)) 
	 */

	arch_send_wakeup_ipi_mask(cpumask_of(cpu));



	/*

	 * now the secondary core is starting up let it run its

	 * calibrations, then wait for it to finish

	 */

	spin_unlock(&boot_lock);



	return ret;

}
@@ -334,7 +311,6 @@ static void __init qcom_smp_prepare_cpus(unsigned int max_cpus) 


static const struct smp_operations smp_msm8660_ops __initconst = {

	.smp_prepare_cpus	= qcom_smp_prepare_cpus,

	.smp_secondary_init	= qcom_secondary_init,

	.smp_boot_secondary	= msm8660_boot_secondary,

#ifdef CONFIG_HOTPLUG_CPU

	.cpu_die		= qcom_cpu_die,
@@ -344,7 +320,6 @@ CPU_METHOD_OF_DECLARE(qcom_smp, "qcom,gcc-msm8660", &smp_msm8660_ops); 


static const struct smp_operations qcom_smp_kpssv1_ops __initconst = {

	.smp_prepare_cpus	= qcom_smp_prepare_cpus,

	.smp_secondary_init	= qcom_secondary_init,

	.smp_boot_secondary	= kpssv1_boot_secondary,

#ifdef CONFIG_HOTPLUG_CPU

	.cpu_die		= qcom_cpu_die,
@@ -354,7 +329,6 @@ CPU_METHOD_OF_DECLARE(qcom_smp_kpssv1, "qcom,kpss-acc-v1", &qcom_smp_kpssv1_ops) 


static const struct smp_operations qcom_smp_kpssv2_ops __initconst = {

	.smp_prepare_cpus	= qcom_smp_prepare_cpus,

	.smp_secondary_init	= qcom_secondary_init,

	.smp_boot_secondary	= kpssv2_boot_secondary,

#ifdef CONFIG_HOTPLUG_CPU

	.cpu_die		= qcom_cpu_die,

CRA Git | Maintained and supported by SUSTech CRA and CCSE