Commit d0e1f211 authored May 30, 2019 by Nick Hu Committed by Paul Walmsley Jun 11, 2019

riscv: Fix udelay in RV32.



In RV32, udelay would delay the wrong cycle. When it shifts right
"UDELAY_SHIFT" bits, it either delays 0 cycle or 1 cycle. It only works
correctly in RV64. Because the 'ucycles' always needs to be 64 bits
variable.

Signed-off-by: Nick Hu <nickhu@andestech.com>
Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
[paul.walmsley@sifive.com: fixed minor spelling error]
Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>

parent 40594558

arch/riscv/lib/delay.c

+1 −1

Original line number	Diff line number	Diff line
		@@ -88,7 +88,7 @@ EXPORT_SYMBOL(__delay);

		void udelay(unsigned long usecs)
		{
		unsigned long ucycles = usecs * lpj_fine * UDELAY_MULT;
		u64 ucycles = (u64)usecs * lpj_fine * UDELAY_MULT;

		if (unlikely(usecs > MAX_UDELAY_US)) {
		__delay((u64)usecs * riscv_timebase / 1000000ULL);

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