Commit d0d6c524 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge branch 'msm-next' of git://people.freedesktop.org/~robclark/linux into drm-next 

Main pull for 3.19.  I may have another pull in a few days with some
mdp5 bits (and hopefully mdp5 atomic), but I figured there was no need
to hold up what we have already.  Main highlights so far:

1) a4xx gpu support (userspace gallium bits on mesa master)
2) mdp4/hdmi/core bits for atomic helpers.  Still missing mdp5
conversion, main hold up there is current hard-coded mixer setup isn't
clever enough to deal with disabling primary plane while crtc active.
3) various other misc cleanup/fixes/etc..

* 'msm-next' of git://people.freedesktop.org/~robclark/linux: (21 commits)
  drm/msm: a4xx support for msm-drm
  drm/msm: Handle register offset differences between a3xx and a4xx
  drm/msm: small mmap offset cleanups
  drm/msm/mdp4: atomic
  drm/msm/hdmi: atomic
  drm/msm: atomic core bits
  drm/msm: bit of fb error checking
  drm/msm: fb prepare/cleanup
  drm/msm: remove unused compile-test stub
  drm/msm: small fence cleanup
  drm/msm/mdp5: drop attached planes table
  drm/msm/mdp4: drop attached planes table
  drm/msm/mdp4: don't care about fb in crtc
  drm/msm/mdp5: drop private primary ptr
  drm/msm/mdp4: drop private primary ptr
  drm/msm: Fix fbdev for 16- and 24-bit modes.
  drm/msm: Allow exported dma-bufs to be mapped
  drm/msm/hdmi: refactor bind/init
  drm/msm: update generated headers
  drm/msm/adreno: slight init order cleanup
  ...
parents 967b8e04 23bd62fd

drivers/gpu/drm/msm/Kconfig

+1 −0
Original line number Diff line number Diff line
@@ -3,6 +3,7 @@ config DRM_MSM 
	tristate "MSM DRM"

	depends on DRM

	depends on ARCH_QCOM || (ARM && COMPILE_TEST)

	select REGULATOR

	select DRM_KMS_HELPER

	select DRM_PANEL

	select SHMEM

drivers/gpu/drm/msm/Makefile

+2 −0
Original line number Diff line number Diff line
@@ -7,6 +7,7 @@ msm-y := \ 
	adreno/adreno_device.o \

	adreno/adreno_gpu.o \

	adreno/a3xx_gpu.o \

	adreno/a4xx_gpu.o \

	hdmi/hdmi.o \

	hdmi/hdmi_audio.o \

	hdmi/hdmi_bridge.o \
@@ -30,6 +31,7 @@ msm-y := \ 
	mdp/mdp5/mdp5_kms.o \

	mdp/mdp5/mdp5_plane.o \

	mdp/mdp5/mdp5_smp.o \

	msm_atomic.o \

	msm_drv.o \

	msm_fb.o \

	msm_gem.o \

drivers/gpu/drm/msm/adreno/a2xx.xml.h

+13 −13
Original line number Diff line number Diff line
@@ -11,10 +11,10 @@ The rules-ng-ng source files this header was generated from are: 
- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml               (    364 bytes, from 2013-11-30 14:47:15)

- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml  (   1453 bytes, from 2013-03-31 16:51:27)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml          (  32901 bytes, from 2014-06-02 15:21:30)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml (   9859 bytes, from 2014-06-02 15:21:30)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml    (  14960 bytes, from 2014-07-27 17:22:13)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml          (  58020 bytes, from 2014-08-01 12:22:48)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml          (  41068 bytes, from 2014-08-01 12:22:48)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml (  10551 bytes, from 2014-11-13 22:44:30)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml    (  15053 bytes, from 2014-11-09 15:45:47)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml          (  63169 bytes, from 2014-11-13 22:44:18)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml          (  49097 bytes, from 2014-11-14 15:38:00)



Copyright (C) 2013-2014 by the following authors:

- Rob Clark <robdclark@gmail.com> (robclark)
@@ -926,11 +926,11 @@ static inline uint32_t A2XX_VGT_DRAW_INITIATOR_INDEX_SIZE(enum pc_di_index_size 
#define A2XX_VGT_DRAW_INITIATOR_NOT_EOP				0x00001000

#define A2XX_VGT_DRAW_INITIATOR_SMALL_INDEX			0x00002000

#define A2XX_VGT_DRAW_INITIATOR_PRE_DRAW_INITIATOR_ENABLE	0x00004000

#define A2XX_VGT_DRAW_INITIATOR_NUM_INDICES__MASK		0xffff0000

#define A2XX_VGT_DRAW_INITIATOR_NUM_INDICES__SHIFT		16

static inline uint32_t A2XX_VGT_DRAW_INITIATOR_NUM_INDICES(uint32_t val)

#define A2XX_VGT_DRAW_INITIATOR_NUM_INSTANCES__MASK		0xff000000

#define A2XX_VGT_DRAW_INITIATOR_NUM_INSTANCES__SHIFT		24

static inline uint32_t A2XX_VGT_DRAW_INITIATOR_NUM_INSTANCES(uint32_t val)

{

	return ((val) << A2XX_VGT_DRAW_INITIATOR_NUM_INDICES__SHIFT) & A2XX_VGT_DRAW_INITIATOR_NUM_INDICES__MASK;

	return ((val) << A2XX_VGT_DRAW_INITIATOR_NUM_INSTANCES__SHIFT) & A2XX_VGT_DRAW_INITIATOR_NUM_INSTANCES__MASK;

}



#define REG_A2XX_VGT_IMMED_DATA					0x000021fd
@@ -1243,13 +1243,13 @@ static inline uint32_t A2XX_CLEAR_COLOR_ALPHA(uint32_t val) 
#define A2XX_PA_SU_POINT_SIZE_HEIGHT__SHIFT			0

static inline uint32_t A2XX_PA_SU_POINT_SIZE_HEIGHT(float val)

{

	return ((((uint32_t)(val * 8.0))) << A2XX_PA_SU_POINT_SIZE_HEIGHT__SHIFT) & A2XX_PA_SU_POINT_SIZE_HEIGHT__MASK;

	return ((((uint32_t)(val * 16.0))) << A2XX_PA_SU_POINT_SIZE_HEIGHT__SHIFT) & A2XX_PA_SU_POINT_SIZE_HEIGHT__MASK;

}

#define A2XX_PA_SU_POINT_SIZE_WIDTH__MASK			0xffff0000

#define A2XX_PA_SU_POINT_SIZE_WIDTH__SHIFT			16

static inline uint32_t A2XX_PA_SU_POINT_SIZE_WIDTH(float val)

{

	return ((((uint32_t)(val * 8.0))) << A2XX_PA_SU_POINT_SIZE_WIDTH__SHIFT) & A2XX_PA_SU_POINT_SIZE_WIDTH__MASK;

	return ((((uint32_t)(val * 16.0))) << A2XX_PA_SU_POINT_SIZE_WIDTH__SHIFT) & A2XX_PA_SU_POINT_SIZE_WIDTH__MASK;

}



#define REG_A2XX_PA_SU_POINT_MINMAX				0x00002281
@@ -1257,13 +1257,13 @@ static inline uint32_t A2XX_PA_SU_POINT_SIZE_WIDTH(float val) 
#define A2XX_PA_SU_POINT_MINMAX_MIN__SHIFT			0

static inline uint32_t A2XX_PA_SU_POINT_MINMAX_MIN(float val)

{

	return ((((uint32_t)(val * 8.0))) << A2XX_PA_SU_POINT_MINMAX_MIN__SHIFT) & A2XX_PA_SU_POINT_MINMAX_MIN__MASK;

	return ((((uint32_t)(val * 16.0))) << A2XX_PA_SU_POINT_MINMAX_MIN__SHIFT) & A2XX_PA_SU_POINT_MINMAX_MIN__MASK;

}

#define A2XX_PA_SU_POINT_MINMAX_MAX__MASK			0xffff0000

#define A2XX_PA_SU_POINT_MINMAX_MAX__SHIFT			16

static inline uint32_t A2XX_PA_SU_POINT_MINMAX_MAX(float val)

{

	return ((((uint32_t)(val * 8.0))) << A2XX_PA_SU_POINT_MINMAX_MAX__SHIFT) & A2XX_PA_SU_POINT_MINMAX_MAX__MASK;

	return ((((uint32_t)(val * 16.0))) << A2XX_PA_SU_POINT_MINMAX_MAX__SHIFT) & A2XX_PA_SU_POINT_MINMAX_MAX__MASK;

}



#define REG_A2XX_PA_SU_LINE_CNTL				0x00002282
@@ -1271,7 +1271,7 @@ static inline uint32_t A2XX_PA_SU_POINT_MINMAX_MAX(float val) 
#define A2XX_PA_SU_LINE_CNTL_WIDTH__SHIFT			0

static inline uint32_t A2XX_PA_SU_LINE_CNTL_WIDTH(float val)

{

	return ((((uint32_t)(val * 8.0))) << A2XX_PA_SU_LINE_CNTL_WIDTH__SHIFT) & A2XX_PA_SU_LINE_CNTL_WIDTH__MASK;

	return ((((uint32_t)(val * 16.0))) << A2XX_PA_SU_LINE_CNTL_WIDTH__SHIFT) & A2XX_PA_SU_LINE_CNTL_WIDTH__MASK;

}



#define REG_A2XX_PA_SC_LINE_STIPPLE				0x00002283

drivers/gpu/drm/msm/adreno/a3xx.xml.h

+221 −26

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drivers/gpu/drm/msm/adreno/a3xx_gpu.c

+91 −0

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