Commit d0a77454 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'fixes' of http://ftp.arm.linux.org.uk/pub/linux/arm/kernel/git-cur/linux-2.6-arm 

* 'fixes' of http://ftp.arm.linux.org.uk/pub/linux/arm/kernel/git-cur/linux-2.6-arm:
  ARM: 7088/1: entry: fix wrong parameter name used in do_thumb_abort
  ARM: 7080/1: l2x0: make sure I&D are not locked down on init
  ARM: 7081/1: mach-integrator: fix the clocksource
  NET: am79c961: fix race in link status code
  ARM: 7067/1: mm: keep significant bits in pfn_valid
parents c338bfb5 6c6d8deb

arch/arm/include/asm/hardware/cache-l2x0.h

+7 −2
Original line number Diff line number Diff line
@@ -45,8 +45,13 @@ 
#define L2X0_CLEAN_INV_LINE_PA		0x7F0

#define L2X0_CLEAN_INV_LINE_IDX		0x7F8

#define L2X0_CLEAN_INV_WAY		0x7FC

#define L2X0_LOCKDOWN_WAY_D		0x900

#define L2X0_LOCKDOWN_WAY_I		0x904

/*

 * The lockdown registers repeat 8 times for L310, the L210 has only one

 * D and one I lockdown register at 0x0900 and 0x0904.

 */

#define L2X0_LOCKDOWN_WAY_D_BASE	0x900

#define L2X0_LOCKDOWN_WAY_I_BASE	0x904

#define L2X0_LOCKDOWN_STRIDE		0x08

#define L2X0_TEST_OPERATION		0xF00

#define L2X0_LINE_DATA			0xF10

#define L2X0_LINE_TAG			0xF30

arch/arm/mach-integrator/integrator_ap.c

+3 −3
Original line number Diff line number Diff line
@@ -337,15 +337,15 @@ static unsigned long timer_reload; 
static void integrator_clocksource_init(u32 khz)

{

	void __iomem *base = (void __iomem *)TIMER2_VA_BASE;

	u32 ctrl = TIMER_CTRL_ENABLE;

	u32 ctrl = TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC;



	if (khz >= 1500) {

		khz /= 16;

		ctrl = TIMER_CTRL_DIV16;

		ctrl |= TIMER_CTRL_DIV16;

	}



	writel(ctrl, base + TIMER_CTRL);

	writel(0xffff, base + TIMER_LOAD);

	writel(ctrl, base + TIMER_CTRL);



	clocksource_mmio_init(base + TIMER_VALUE, "timer2",

		khz * 1000, 200, 16, clocksource_mmio_readl_down);

arch/arm/mm/abort-macro.S

+1 −1
Original line number Diff line number Diff line
@@ -17,7 +17,7 @@ 
	cmp	\tmp, # 0x5600			@ Is it ldrsb?

	orreq	\tmp, \tmp, #1 << 11		@ Set L-bit if yes

	tst	\tmp, #1 << 11			@ L = 0 -> write

	orreq	\psr, \psr, #1 << 11		@ yes.

	orreq	\fsr, \fsr, #1 << 11		@ yes.

	b	do_DataAbort

not_thumb:

	.endm

arch/arm/mm/cache-l2x0.c

+21 −0
Original line number Diff line number Diff line
@@ -277,6 +277,25 @@ static void l2x0_disable(void) 
	spin_unlock_irqrestore(&l2x0_lock, flags);

}



static void __init l2x0_unlock(__u32 cache_id)

{

	int lockregs;

	int i;



	if (cache_id == L2X0_CACHE_ID_PART_L310)

		lockregs = 8;

	else

		/* L210 and unknown types */

		lockregs = 1;



	for (i = 0; i < lockregs; i++) {

		writel_relaxed(0x0, l2x0_base + L2X0_LOCKDOWN_WAY_D_BASE +

			       i * L2X0_LOCKDOWN_STRIDE);

		writel_relaxed(0x0, l2x0_base + L2X0_LOCKDOWN_WAY_I_BASE +

			       i * L2X0_LOCKDOWN_STRIDE);

	}

}



void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask)

{

	__u32 aux;
@@ -328,6 +347,8 @@ void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask) 
	 * accessing the below registers will fault.

	 */

	if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & 1)) {

		/* Make sure that I&D is not locked down when starting */

		l2x0_unlock(cache_id);



		/* l2x0 controller is disabled */

		writel_relaxed(aux, l2x0_base + L2X0_AUX_CTRL);

arch/arm/mm/init.c

+1 −1
Original line number Diff line number Diff line
@@ -298,7 +298,7 @@ static void __init arm_bootmem_free(unsigned long min, unsigned long max_low, 
#ifdef CONFIG_HAVE_ARCH_PFN_VALID

int pfn_valid(unsigned long pfn)

{

	return memblock_is_memory(pfn << PAGE_SHIFT);

	return memblock_is_memory(__pfn_to_phys(pfn));

}

EXPORT_SYMBOL(pfn_valid);

#endif

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