Commit d09fca9e authored by Bjorn Helgaas's avatar Bjorn Helgaas
Browse files

Merge branch 'remotes/lorenzo/pci/mobiveil' 

  - Restructure mobiveil driver to support either Root Complex mode or
    Endpoint mode (Hou Zhiqiang)

  - Collect host initialization into one place (Hou Zhiqiang)

  - Collect interrupt-related code into one place (Hou Zhiqiang)

  - Split mobiveil into separate files under
    drivers/pci/controller/mobiveil for easier reuse (Hou Zhiqiang)

  - Add callbacks for interrupt initialization and linkup checking (Hou
    Zhiqiang)

  - Add 8- and 16-bit CSR accessors (Hou Zhiqiang)

  - Initialize host driver only if Header Type is "bridge" (Hou Zhiqiang)

  - Add DT bindings for NXP Layerscape SoCs PCIe Gen4 controller (Hou
    Zhiqiang)

  - Add PCIe Gen4 RC driver for Layerscape SoCs (Hou Zhiqiang)

  - Add pcie-mobiveil __iomem annotations (Hou Zhiqiang)

  - Add PCI_MSI_IRQ_DOMAIN Kconfig dependency (Hou Zhiqiang)

* remotes/lorenzo/pci/mobiveil:
  PCI: mobiveil: Fix unmet dependency warning for PCIE_MOBIVEIL_PLAT
  PCI: mobiveil: Fix sparse different address space warnings
  PCI: mobiveil: Add PCIe Gen4 RC driver for Layerscape SoCs
  dt-bindings: PCI: Add NXP Layerscape SoCs PCIe Gen4 controller
  PCI: mobiveil: Add Header Type field check
  PCI: mobiveil: Add 8-bit and 16-bit CSR register accessors
  PCI: mobiveil: Allow mobiveil_host_init() to be used to re-init host
  PCI: mobiveil: Add callback function for link up check
  PCI: mobiveil: Add callback function for interrupt initialization
  PCI: mobiveil: Modularize the Mobiveil PCIe Host Bridge IP driver
  PCI: mobiveil: Collect the interrupt related operations into a function
  PCI: mobiveil: Move the host initialization into a function
  PCI: mobiveil: Introduce a new structure mobiveil_root_port
parents a29a44c1 863bba34

Documentation/devicetree/bindings/pci/layerscape-pcie-gen4.txt

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NXP Layerscape PCIe Gen4 controller



This PCIe controller is based on the Mobiveil PCIe IP and thus inherits all

the common properties defined in mobiveil-pcie.txt.



Required properties:

- compatible: should contain the platform identifier such as:

  "fsl,lx2160a-pcie"

- reg: base addresses and lengths of the PCIe controller register blocks.

  "csr_axi_slave": Bridge config registers

  "config_axi_slave": PCIe controller registers

- interrupts: A list of interrupt outputs of the controller. Must contain an

  entry for each entry in the interrupt-names property.

- interrupt-names: It could include the following entries:

  "intr": The interrupt that is asserted for controller interrupts

  "aer": Asserted for aer interrupt when chip support the aer interrupt with

	 none MSI/MSI-X/INTx mode,but there is interrupt line for aer.

  "pme": Asserted for pme interrupt when chip support the pme interrupt with

	 none MSI/MSI-X/INTx mode,but there is interrupt line for pme.

- dma-coherent: Indicates that the hardware IP block can ensure the coherency

  of the data transferred from/to the IP block. This can avoid the software

  cache flush/invalid actions, and improve the performance significantly.

- msi-parent : See the generic MSI binding described in

  Documentation/devicetree/bindings/interrupt-controller/msi.txt.



Example:



	pcie@3400000 {

		compatible = "fsl,lx2160a-pcie";

		reg = <0x00 0x03400000 0x0 0x00100000   /* controller registers */

		       0x80 0x00000000 0x0 0x00001000>; /* configuration space */

		reg-names = "csr_axi_slave", "config_axi_slave";

		interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */

			     <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */

			     <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */

		interrupt-names = "aer", "pme", "intr";

		#address-cells = <3>;

		#size-cells = <2>;

		device_type = "pci";

		apio-wins = <8>;

		ppio-wins = <8>;

		dma-coherent;

		bus-range = <0x0 0xff>;

		msi-parent = <&its>;

		ranges = <0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>;

		#interrupt-cells = <1>;

		interrupt-map-mask = <0 0 0 7>;

		interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,

				<0000 0 0 2 &gic 0 0 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,

				<0000 0 0 3 &gic 0 0 GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,

				<0000 0 0 4 &gic 0 0 GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;

	};

MAINTAINERS

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@@ -12752,6 +12752,14 @@ L: linux-arm-kernel@lists.infradead.org 
S:	Maintained

F:	drivers/pci/controller/dwc/*layerscape*













PCI DRIVER FOR NXP LAYERSCAPE GEN4 CONTROLLER













M:	Hou Zhiqiang <Zhiqiang.Hou@nxp.com>













L:	linux-pci@vger.kernel.org













L:	linux-arm-kernel@lists.infradead.org













S:	Maintained













F:	Documentation/devicetree/bindings/pci/layerscape-pcie-gen4.txt













F:	drivers/pci/controller/mobibeil/pcie-layerscape-gen4.c



























PCI DRIVER FOR GENERIC OF HOSTS















M:	Will Deacon <will@kernel.org>















L:	linux-pci@vger.kernel.org










@@ -12794,7 +12802,7 @@ M:	Hou Zhiqiang <Zhiqiang.Hou@nxp.com>













L:	linux-pci@vger.kernel.org















S:	Supported















F:	Documentation/devicetree/bindings/pci/mobiveil-pcie.txt













F:	drivers/pci/controller/pcie-mobiveil.c













F:	drivers/pci/controller/mobiveil/pcie-mobiveil*





























PCI DRIVER FOR MVEBU (Marvell Armada 370 and Armada XP SOC support)















M:	Thomas Petazzoni <thomas.petazzoni@bootlin.com>

































drivers/pci/controller/Kconfig



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@@ -213,16 +213,6 @@ config PCIE_MEDIATEK













	  Say Y here if you want to enable PCIe controller support on















	  MediaTek SoCs.





























config PCIE_MOBIVEIL













	bool "Mobiveil AXI PCIe controller"













	depends on ARCH_ZYNQMP || COMPILE_TEST













	depends on OF













	depends on PCI_MSI_IRQ_DOMAIN













	help













	  Say Y here if you want to enable support for the Mobiveil AXI PCIe













	  Soft IP. It has up to 8 outbound and inbound windows













	  for address translation and it is a PCIe Gen4 IP.





























config PCIE_TANGO_SMP8759















	bool "Tango SMP8759 PCIe controller (DANGEROUS)"















	depends on ARCH_TANGO && PCI_MSI && OF










@@ -269,5 +259,6 @@ config PCI_HYPERV_INTERFACE













	  have a common interface with the Hyper-V PCI frontend driver.































source "drivers/pci/controller/dwc/Kconfig"













source "drivers/pci/controller/mobiveil/Kconfig"















source "drivers/pci/controller/cadence/Kconfig"















endmenu
























drivers/pci/controller/Makefile



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@@ -25,12 +25,12 @@ obj-$(CONFIG_PCIE_ROCKCHIP) += pcie-rockchip.o













obj-$(CONFIG_PCIE_ROCKCHIP_EP) += pcie-rockchip-ep.o















obj-$(CONFIG_PCIE_ROCKCHIP_HOST) += pcie-rockchip-host.o















obj-$(CONFIG_PCIE_MEDIATEK) += pcie-mediatek.o













obj-$(CONFIG_PCIE_MOBIVEIL) += pcie-mobiveil.o















obj-$(CONFIG_PCIE_TANGO_SMP8759) += pcie-tango.o















obj-$(CONFIG_VMD) += vmd.o















obj-$(CONFIG_PCIE_BRCMSTB) += pcie-brcmstb.o















# pcie-hisi.o quirks are needed even without CONFIG_PCIE_DW















obj-y				+= dwc/













obj-y				+= mobiveil/















































# The following drivers are for devices that use the generic ACPI

































drivers/pci/controller/mobiveil/Kconfig
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# SPDX-License-Identifier: GPL-2.0



























menu "Mobiveil PCIe Core Support"













	depends on PCI



























config PCIE_MOBIVEIL













	bool



























config PCIE_MOBIVEIL_HOST













	bool













	depends on PCI_MSI_IRQ_DOMAIN













	select PCIE_MOBIVEIL



























config PCIE_MOBIVEIL_PLAT













	bool "Mobiveil AXI PCIe controller"













	depends on ARCH_ZYNQMP || COMPILE_TEST













	depends on OF













	depends on PCI_MSI_IRQ_DOMAIN













	select PCIE_MOBIVEIL_HOST













	help













	  Say Y here if you want to enable support for the Mobiveil AXI PCIe













	  Soft IP. It has up to 8 outbound and inbound windows













	  for address translation and it is a PCIe Gen4 IP.



























config PCIE_LAYERSCAPE_GEN4













	bool "Freescale Layerscape PCIe Gen4 controller"













	depends on PCI













	depends on OF && (ARM64 || ARCH_LAYERSCAPE)













	depends on PCI_MSI_IRQ_DOMAIN













	select PCIE_MOBIVEIL_HOST













	help













	  Say Y here if you want PCIe Gen4 controller support on













	  Layerscape SoCs.













endmenu
































































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