Commit d0766e98 authored by Zhang, Jerry's avatar Zhang, Jerry Committed by Alex Deucher
Browse files

drm/amdgpu: PRT support for gfx9 (v3) 



Fix PRT handling on gfx9

v2: unify PRT bit for all ASICs
v3: move PRT flag checking in amdgpu_vm_bo_split_mapping()

Signed-off-by: default avatarJunwei Zhang <Jerry.Zhang@amd.com>
Acked-by: default avatarDavid Zhou <david1.zhou@amd.com>
Reviewed-by: default avatarChristian König <christian.koenig@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent fc6aa33d

drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c

+6 −0
Original line number Diff line number Diff line
@@ -1338,6 +1338,12 @@ static int amdgpu_vm_bo_split_mapping(struct amdgpu_device *adev, 
	flags &= ~AMDGPU_PTE_MTYPE_MASK;

	flags |= (mapping->flags & AMDGPU_PTE_MTYPE_MASK);



	if ((mapping->flags & AMDGPU_PTE_PRT) &&

	    (adev->asic_type >= CHIP_VEGA10)) {

		flags |= AMDGPU_PTE_PRT;

		flags &= ~AMDGPU_PTE_VALID;

	}



	trace_amdgpu_vm_bo_update(mapping);



	pfn = mapping->offset >> PAGE_SHIFT;

drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h

+2 −1
Original line number Diff line number Diff line
@@ -65,7 +65,8 @@ struct amdgpu_bo_list_entry; 


#define AMDGPU_PTE_FRAG(x)	((x & 0x1fULL) << 7)



#define AMDGPU_PTE_PRT		(1ULL << 63)

/* TILED for VEGA10, reserved for older ASICs  */

#define AMDGPU_PTE_PRT		(1ULL << 51)



/* VEGA10 only */

#define AMDGPU_PTE_MTYPE(a)    ((uint64_t)a << 57)

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