Merge tag 'common/for-v5.4-rc1/cpu-topology' of...

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ARM topology binding description

CPU topology binding description

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1 - Introduction

===========================================

In an ARM system, the hierarchy of CPUs is defined through three entities that

In a SMP system, the hierarchy of CPUs is defined through three entities that

are used to describe the layout of physical CPUs in the system:

- socket

- cluster

- core

- thread

The cpu nodes (bindings defined in [1]) represent the devices that

correspond to physical CPUs and are to be mapped to the hierarchy levels.

The bottom hierarchy level sits at core or thread level depending on whether

symmetric multi-threading (SMT) is supported or not.

In systems where SMT is not supported "cpu" nodes represent all cores present

in the system and map to the hierarchy level "core" above.

ARM topology bindings allow one to associate cpu nodes with hierarchical groups

CPU topology bindings allow one to associate cpu nodes with hierarchical groups

corresponding to the system hierarchy; syntactically they are defined as device

tree nodes.

The remainder of this document provides the topology bindings for ARM, based

on the Devicetree Specification, available from:

Currently, only ARM/RISC-V intend to use this cpu topology binding but it may be

used for any other architecture as well.

https://www.devicetree.org/specifications/

The cpu nodes, as per bindings defined in [4], represent the devices that

correspond to physical CPUs and are to be mapped to the hierarchy levels.

If not stated otherwise, whenever a reference to a cpu node phandle is made its

value must point to a cpu node compliant with the cpu node bindings as

documented in [1].

A topology description containing phandles to cpu nodes that are not compliant

with bindings standardized in [1] is therefore considered invalid.

with bindings standardized in [4] is therefore considered invalid.

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2 - cpu-map node

===========================================

The ARM CPU topology is defined within the cpu-map node, which is a direct

The ARM/RISC-V CPU topology is defined within the cpu-map node, which is a direct

child of the cpus node and provides a container where the actual topology

nodes are listed.

- cpu-map node

	Usage: Optional - On ARM SMP systems provide CPUs topology to the OS.

			  ARM uniprocessor systems do not require a topology

	Usage: Optional - On SMP systems provide CPUs topology to the OS.

			  Uniprocessor systems do not require a topology

			  description and therefore should not define a

			  cpu-map node.

	The cpu-map node's child nodes can be:

	- one or more cluster nodes

	- one or more cluster nodes or

	- one or more socket nodes in a multi-socket system

	Any other configuration is considered invalid.

The cpu-map node can only contain three types of child nodes:

The cpu-map node can only contain 4 types of child nodes:

- socket node

- cluster node

- core node

- thread node

whose bindings are described in paragraph 3.

The nodes describing the CPU topology (cluster/core/thread) can only

be defined within the cpu-map node and every core/thread in the system

must be defined within the topology.  Any other configuration is

The nodes describing the CPU topology (socket/cluster/core/thread) can

only be defined within the cpu-map node and every core/thread in the

system must be defined within the topology.  Any other configuration is

invalid and therefore must be ignored.

===========================================

===========================================

cpu-map child nodes must follow a naming convention where the node name

must be "clusterN", "coreN", "threadN" depending on the node type (ie

cluster/core/thread) (where N = {0, 1, ...} is the node number; nodes which

are siblings within a single common parent node must be given a unique and

must be "socketN", "clusterN", "coreN", "threadN" depending on the node type

(ie socket/cluster/core/thread) (where N = {0, 1, ...} is the node number; nodes

which are siblings within a single common parent node must be given a unique and

sequential N value, starting from 0).

cpu-map child nodes which do not share a common parent node can have the same

name (ie same number N as other cpu-map child nodes at different device tree

levels) since name uniqueness will be guaranteed by the device tree hierarchy.

===========================================

3 - cluster/core/thread node bindings

3 - socket/cluster/core/thread node bindings

===========================================

Bindings for cluster/cpu/thread nodes are defined as follows:

Bindings for socket/cluster/cpu/thread nodes are defined as follows:

- socket node

	 Description: must be declared within a cpu-map node, one node

		      per physical socket in the system. A system can

		      contain single or multiple physical socket.

		      The association of sockets and NUMA nodes is beyond

		      the scope of this bindings, please refer [2] for

		      NUMA bindings.

	This node is optional for a single socket system.

	The socket node name must be "socketN" as described in 2.1 above.

	A socket node can not be a leaf node.

	A socket node's child nodes must be one or more cluster nodes.

	Any other configuration is considered invalid.

- cluster node

	 Description: must be declared within a cpu-map node, one node

		      per cluster. A system can contain several layers of

		      clustering and cluster nodes can be contained in parent

		      cluster nodes.

		      clustering within a single physical socket and cluster

		      nodes can be contained in parent cluster nodes.

	The cluster node name must be "clusterN" as described in 2.1 above.

	A cluster node can not be a leaf node.

4 - Example dts

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Example 1 (ARM 64-bit, 16-cpu system, two clusters of clusters):

Example 1 (ARM 64-bit, 16-cpu system, two clusters of clusters in a single

physical socket):

cpus {

	#size-cells = <0>;

	#address-cells = <2>;

	cpu-map {

		socket0 {

			cluster0 {

				cluster0 {

					core0 {

				};

			};

		};

	};

	CPU0: cpu@0 {

		device_type = "cpu";

	};

};

Example 3: HiFive Unleashed (RISC-V 64 bit, 4 core system)

{

	#address-cells = <2>;

	#size-cells = <2>;

	compatible = "sifive,fu540g", "sifive,fu500";

	model = "sifive,hifive-unleashed-a00";

	...

	cpus {

		#address-cells = <1>;

		#size-cells = <0>;

		cpu-map {

			socket0 {

				cluster0 {

					core0 {

						cpu = <&CPU1>;

					};

					core1 {

						cpu = <&CPU2>;

					};

					core2 {

						cpu0 = <&CPU2>;

					};

					core3 {

						cpu0 = <&CPU3>;

					};

				};

			};

		};

		CPU1: cpu@1 {

			device_type = "cpu";

			compatible = "sifive,rocket0", "riscv";

			reg = <0x1>;

		}

		CPU2: cpu@2 {

			device_type = "cpu";

			compatible = "sifive,rocket0", "riscv";

			reg = <0x2>;

		}

		CPU3: cpu@3 {

			device_type = "cpu";

			compatible = "sifive,rocket0", "riscv";

			reg = <0x3>;

		}

		CPU4: cpu@4 {

			device_type = "cpu";

			compatible = "sifive,rocket0", "riscv";

			reg = <0x4>;

		}

	}

};

===============================================================================

[1] ARM Linux kernel documentation

    Documentation/devicetree/bindings/arm/cpus.yaml

[2] Devicetree NUMA binding description

    Documentation/devicetree/bindings/numa.txt

[3] RISC-V Linux kernel documentation

    Documentation/devicetree/bindings/riscv/cpus.txt

[4] https://www.devicetree.org/specifications/

S:	Maintained

F:	drivers/media/radio/radio-gemtek*

GENERIC ARCHITECTURE TOPOLOGY

M:	Sudeep Holla <sudeep.holla@arm.com>

L:	linux-kernel@vger.kernel.org

S:	Maintained

F:	drivers/base/arch_topology.c

F:	include/linux/arch_topology.h

GENERIC GPIO I2C DRIVER

M:	Wolfram Sang <wsa+renesas@sang-engineering.com>

S:	Supported

#ifdef CONFIG_ARM_CPU_TOPOLOGY

#include <linux/cpumask.h>

struct cputopo_arm {

	int thread_id;

	int core_id;

	int socket_id;

	cpumask_t thread_sibling;

	cpumask_t core_sibling;

};

extern struct cputopo_arm cpu_topology[NR_CPUS];

#define topology_physical_package_id(cpu)	(cpu_topology[cpu].socket_id)

#define topology_core_id(cpu)		(cpu_topology[cpu].core_id)

#define topology_core_cpumask(cpu)	(&cpu_topology[cpu].core_sibling)

#define topology_sibling_cpumask(cpu)	(&cpu_topology[cpu].thread_sibling)

void init_cpu_topology(void);

void store_cpu_topology(unsigned int cpuid);

const struct cpumask *cpu_coregroup_mask(int cpu);

#include <linux/arch_topology.h>

/* Replace task scheduler's default frequency-invariant accounting */

static inline void update_cpu_capacity(unsigned int cpuid) {}

#endif

 /*

 * cpu topology table

 */

struct cputopo_arm cpu_topology[NR_CPUS];

EXPORT_SYMBOL_GPL(cpu_topology);

const struct cpumask *cpu_coregroup_mask(int cpu)

{

	return &cpu_topology[cpu].core_sibling;

}

/*

 * The current assumption is that we can power gate each core independently.

 * This will be superseded by DT binding once available.

	return &cpu_topology[cpu].thread_sibling;

}

static void update_siblings_masks(unsigned int cpuid)

{

	struct cputopo_arm *cpu_topo, *cpuid_topo = &cpu_topology[cpuid];

	int cpu;

	/* update core and thread sibling masks */

	for_each_possible_cpu(cpu) {

		cpu_topo = &cpu_topology[cpu];

		if (cpuid_topo->socket_id != cpu_topo->socket_id)

			continue;

		cpumask_set_cpu(cpuid, &cpu_topo->core_sibling);

		if (cpu != cpuid)

			cpumask_set_cpu(cpu, &cpuid_topo->core_sibling);

		if (cpuid_topo->core_id != cpu_topo->core_id)

			continue;

		cpumask_set_cpu(cpuid, &cpu_topo->thread_sibling);

		if (cpu != cpuid)

			cpumask_set_cpu(cpu, &cpuid_topo->thread_sibling);

	}

	smp_wmb();

}

/*

 * store_cpu_topology is called at boot when only one cpu is running

 * and with the mutex cpu_hotplug.lock locked, when several cpus have booted,

 */

void store_cpu_topology(unsigned int cpuid)

{

	struct cputopo_arm *cpuid_topo = &cpu_topology[cpuid];

	struct cpu_topology *cpuid_topo = &cpu_topology[cpuid];

	unsigned int mpidr;

	/* If the cpu topology has been already set, just return */

			/* core performance interdependency */

			cpuid_topo->thread_id = MPIDR_AFFINITY_LEVEL(mpidr, 0);

			cpuid_topo->core_id = MPIDR_AFFINITY_LEVEL(mpidr, 1);

			cpuid_topo->socket_id = MPIDR_AFFINITY_LEVEL(mpidr, 2);

			cpuid_topo->package_id = MPIDR_AFFINITY_LEVEL(mpidr, 2);

		} else {

			/* largely independent cores */

			cpuid_topo->thread_id = -1;

			cpuid_topo->core_id = MPIDR_AFFINITY_LEVEL(mpidr, 0);

			cpuid_topo->socket_id = MPIDR_AFFINITY_LEVEL(mpidr, 1);

			cpuid_topo->package_id = MPIDR_AFFINITY_LEVEL(mpidr, 1);

		}

	} else {

		/*

		 */

		cpuid_topo->thread_id = -1;

		cpuid_topo->core_id = 0;

		cpuid_topo->socket_id = -1;

		cpuid_topo->package_id = -1;

	}

	update_siblings_masks(cpuid);

	pr_info("CPU%u: thread %d, cpu %d, socket %d, mpidr %x\n",

		cpuid, cpu_topology[cpuid].thread_id,

		cpu_topology[cpuid].core_id,

		cpu_topology[cpuid].socket_id, mpidr);

		cpu_topology[cpuid].package_id, mpidr);

}

static inline int cpu_corepower_flags(void)

 */

void __init init_cpu_topology(void)

{

	unsigned int cpu;

	/* init core mask and capacity */

	for_each_possible_cpu(cpu) {

		struct cputopo_arm *cpu_topo = &(cpu_topology[cpu]);

		cpu_topo->thread_id = -1;

		cpu_topo->core_id =  -1;

		cpu_topo->socket_id = -1;

		cpumask_clear(&cpu_topo->core_sibling);

		cpumask_clear(&cpu_topo->thread_sibling);

	}

	reset_cpu_topology();

	smp_wmb();

	parse_dt_topology();

#include <linux/cpumask.h>

struct cpu_topology {

	int thread_id;

	int core_id;

	int package_id;

	int llc_id;

	cpumask_t thread_sibling;

	cpumask_t core_sibling;

	cpumask_t llc_sibling;

};

extern struct cpu_topology cpu_topology[NR_CPUS];

#define topology_physical_package_id(cpu)	(cpu_topology[cpu].package_id)

#define topology_core_id(cpu)		(cpu_topology[cpu].core_id)

#define topology_core_cpumask(cpu)	(&cpu_topology[cpu].core_sibling)

#define topology_sibling_cpumask(cpu)	(&cpu_topology[cpu].thread_sibling)

#define topology_llc_cpumask(cpu)	(&cpu_topology[cpu].llc_sibling)

void init_cpu_topology(void);

void store_cpu_topology(unsigned int cpuid);

void remove_cpu_topology(unsigned int cpuid);

const struct cpumask *cpu_coregroup_mask(int cpu);

#ifdef CONFIG_NUMA

struct pci_bus;