Commit d056a699 authored Dec 19, 2012 by Will Deacon Committed by Russell King Dec 20, 2012

ARM: 7606/1: cache: flush to LoUU instead of LoUIS on uniprocessor CPUs

flush_cache_louis flushes the D-side caches to the point of unification
inner-shareable. On uniprocessor CPUs, this is defined as zero and
therefore no flushing will take place. Rather than invent a new interface
for UP systems, instead use our SMP_ON_UP patching code to read the
LoUU from the CLIDR instead.

Cc: <stable@vger.kernel.org>
Cc: Lorenzo Pieralisi <Lorenzo.Pieralisi@arm.com>
Tested-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

parent 7bf9b7be

arch/arm/mm/cache-v7.S

+4 −2

Original line number	Diff line number	Diff line
		@@ -44,8 +44,10 @@ ENDPROC(v7_flush_icache_all)
		ENTRY(v7_flush_dcache_louis)
		dmb @ ensure ordering with previous memory accesses
		mrc p15, 1, r0, c0, c0, 1 @ read clidr, r0 = clidr
		ands r3, r0, #0xe00000 @ extract LoUIS from clidr
		mov r3, r3, lsr #20 @ r3 = LoUIS * 2
		ALT_SMP(ands r3, r0, #(7 << 21)) @ extract LoUIS from clidr
		ALT_UP(ands r3, r0, #(7 << 27)) @ extract LoUU from clidr
		ALT_SMP(mov r3, r3, lsr #20) @ r3 = LoUIS * 2
		ALT_UP(mov r3, r3, lsr #26) @ r3 = LoUU * 2
		moveq pc, lr @ return if level == 0
		mov r10, #0 @ r10 (starting level) = 0
		b flush_levels @ start flushing cache levels

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