arm64: dts: allwinner: h5: Add trip and cooling maps to CPU thermal zones (d04f7bc8) · Commits · 戴 / test

arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi

+30 −0

Original line number	Diff line number	Diff line
		@@ -3,6 +3,8 @@

		#include <arm/sunxi-h3-h5.dtsi>

		#include <dt-bindings/thermal/thermal.h>

		/ {
		cpus {
		#address-cells = <1>;
		@@ -15,6 +17,7 @@
		enable-method = "psci";
		clocks = <&ccu CLK_CPUX>;
		clock-latency-ns = <244144>; /* 8 32k periods */
		#cooling-cells = <2>;
		};

		cpu1: cpu@1 {
		@@ -24,6 +27,7 @@
		enable-method = "psci";
		clocks = <&ccu CLK_CPUX>;
		clock-latency-ns = <244144>; /* 8 32k periods */
		#cooling-cells = <2>;
		};

		cpu2: cpu@2 {
		@@ -33,6 +37,7 @@
		enable-method = "psci";
		clocks = <&ccu CLK_CPUX>;
		clock-latency-ns = <244144>; /* 8 32k periods */
		#cooling-cells = <2>;
		};

		cpu3: cpu@3 {
		@@ -42,6 +47,7 @@
		enable-method = "psci";
		clocks = <&ccu CLK_CPUX>;
		clock-latency-ns = <244144>; /* 8 32k periods */
		#cooling-cells = <2>;
		};
		};

		@@ -173,6 +179,30 @@
		polling-delay-passive = <0>;
		polling-delay = <0>;
		thermal-sensors = <&ths 0>;

		trips {
		cpu_hot_trip: cpu-hot {
		temperature = <80000>;
		hysteresis = <2000>;
		type = "passive";
		};

		cpu_very_hot_trip: cpu-very-hot {
		temperature = <100000>;
		hysteresis = <0>;
		type = "critical";
		};
		};

		cooling-maps {
		cpu-hot-limit {
		trip = <&cpu_hot_trip>;
		cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
		<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
		<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
		<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
		};
		};
		};

		gpu_thermal {