Commit d01e12dd authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'linus' of git://git.kernel.org/pub/scm/linux/kernel/git/evalenti/linux-soc-thermal 

Pull thermal management updates from Eduardo Valentin:

 - rework tsens driver to add support for tsens-v2 (Amit Kucheria)

 - rework armada thermal driver to use syscon and multichannel support
   (Miquel Raynal)

 - fixes to TI SoC, IMX, Exynos, RCar, and hwmon drivers

* 'linus' of git://git.kernel.org/pub/scm/linux/kernel/git/evalenti/linux-soc-thermal: (34 commits)
  thermal: armada: fix copy-paste error in armada_thermal_probe()
  thermal: rcar_thermal: avoid NULL dereference in absence of IRQ resources
  thermal: samsung: Remove Exynos5440 clock handling left-overs
  thermal: tsens: Fix negative temperature reporting
  thermal: tsens: switch from of_iomap() to devm_ioremap_resource()
  thermal: tsens: Rename variable
  thermal: tsens: Add generic support for TSENS v2 IP
  thermal: tsens: Rename tsens-8996 to tsens-v2 for reuse
  thermal: tsens: Add support to split up register address space into two
  dt: thermal: tsens: Document the fallback DT property for v2 of TSENS IP
  thermal: tsens: Get rid of unused fields in structure
  thermal_hwmon: Pass the originating device down to hwmon_device_register_with_info
  thermal_hwmon: Sanitize attribute name passed to hwmon
  dt-bindings: thermal: armada: add reference to new bindings
  dt-bindings: cp110: add the thermal node in the syscon file
  dt-bindings: cp110: update documentation since DT de-duplication
  dt-bindings: ap806: add the thermal node in the syscon file
  dt-bindings: cp110: prepare the syscon file to list other syscons nodes
  dt-bindings: ap806: prepare the syscon file to list other syscons nodes
  dt-bindings: cp110: rename cp110 syscon file
  ...
parents 9502f0d1 84b64de5

Documentation/devicetree/bindings/arm/marvell/ap806-system-controller.txt

+43 −5
Original line number Diff line number Diff line
@@ -2,15 +2,18 @@ Marvell Armada AP806 System Controller 
======================================



The AP806 is one of the two core HW blocks of the Marvell Armada 7K/8K

SoCs. It contains a system controller, which provides a number

registers giving access to numerous features: clocks, pin-muxing and

many other SoC configuration items. This DT binding allows to describe

this system controller.

SoCs. It contains system controllers, which provide several registers

giving access to numerous features: clocks, pin-muxing and many other

SoC configuration items. This DT binding allows to describe these

system controllers.



For the top level node:

 - compatible: must be: "syscon", "simple-mfd";

 - reg: register area of the AP806 system controller



SYSTEM CONTROLLER 0

===================



Clocks:

-------
@@ -98,3 +101,38 @@ ap_syscon: system-controller@6f4000 { 
		gpio-ranges = <&ap_pinctrl 0 0 19>;

	};

};



SYSTEM CONTROLLER 1

===================



Thermal:

--------



For common binding part and usage, refer to

Documentation/devicetree/bindings/thermal/thermal.txt



The thermal IP can probe the temperature all around the processor. It

may feature several channels, each of them wired to one sensor.



Required properties:

- compatible: must be one of:

  * marvell,armada-ap806-thermal

- reg: register range associated with the thermal functions.



Optional properties:

- #thermal-sensor-cells: shall be <1> when thermal-zones subnodes refer

  to this IP and represents the channel ID. There is one sensor per

  channel. O refers to the thermal IP internal channel, while positive

  IDs refer to each CPU.



Example:

ap_syscon1: system-controller@6f8000 {

	compatible = "syscon", "simple-mfd";

	reg = <0x6f8000 0x1000>;



	ap_thermal: thermal-sensor@80 {

		compatible = "marvell,armada-ap806-thermal";

		reg = <0x80 0x10>;

		#thermal-sensor-cells = <1>;

	};

};

Documentation/devicetree/bindings/arm/marvell/cp110-system-controller0.txt→Documentation/devicetree/bindings/arm/marvell/cp110-system-controller.txt

+49 −12
Original line number Diff line number Diff line 
Marvell Armada CP110 System Controller 0

========================================

Marvell Armada CP110 System Controller

======================================



The CP110 is one of the two core HW blocks of the Marvell Armada 7K/8K

SoCs. It contains two sets of system control registers, System

Controller 0 and System Controller 1. This Device Tree binding allows

to describe the first system controller, which provides registers to

configure various aspects of the SoC.

SoCs. It contains system controllers, which provide several registers

giving access to numerous features: clocks, pin-muxing and many other

SoC configuration items. This DT binding allows to describe these

system controllers.



For the top level node:

 - compatible: must be: "syscon", "simple-mfd";

 - reg: register area of the CP110 system controller 0

 - reg: register area of the CP110 system controller



SYSTEM CONTROLLER 0

===================



Clocks:

-------
@@ -163,26 +166,60 @@ Required properties: 


Example:



cpm_syscon0: system-controller@440000 {

CP110_LABEL(syscon0): system-controller@440000 {

	compatible = "syscon", "simple-mfd";

	reg = <0x440000 0x1000>;



	cpm_clk: clock {

	CP110_LABEL(clk): clock {

		compatible = "marvell,cp110-clock";

		#clock-cells = <2>;

	};



	cpm_pinctrl: pinctrl {

	CP110_LABEL(pinctrl): pinctrl {

		compatible = "marvell,armada-8k-cpm-pinctrl";

	};



	cpm_gpio1: gpio@100 {

	CP110_LABEL(gpio1): gpio@100 {

		compatible = "marvell,armada-8k-gpio";

		offset = <0x100>;

		ngpios = <32>;

		gpio-controller;

		#gpio-cells = <2>;

		gpio-ranges = <&cpm_pinctrl 0 0 32>;

		gpio-ranges = <&CP110_LABEL(pinctrl) 0 0 32>;

	};



};



SYSTEM CONTROLLER 1

===================



Thermal:

--------



The thermal IP can probe the temperature all around the processor. It

may feature several channels, each of them wired to one sensor.



For common binding part and usage, refer to

Documentation/devicetree/bindings/thermal/thermal.txt



Required properties:

- compatible: must be one of:

  * marvell,armada-cp110-thermal

- reg: register range associated with the thermal functions.



Optional properties:

- #thermal-sensor-cells: shall be <1> when thermal-zones subnodes refer

  to this IP and represents the channel ID. There is one sensor per

  channel. O refers to the thermal IP internal channel.



Example:

CP110_LABEL(syscon1): system-controller@6f8000 {

	compatible = "syscon", "simple-mfd";

	reg = <0x6f8000 0x1000>;



	CP110_LABEL(thermal): thermal-sensor@70 {

		compatible = "marvell,armada-cp110-thermal";

		reg = <0x70 0x10>;

		#thermal-sensor-cells = <1>;

	};

};

Documentation/devicetree/bindings/thermal/armada-thermal.txt

+5 −0
Original line number Diff line number Diff line
@@ -10,6 +10,11 @@ Required properties: 
    * marvell,armada-ap806-thermal

    * marvell,armada-cp110-thermal



Note: these bindings are deprecated for AP806/CP110 and should instead

follow the rules described in:

Documentation/devicetree/bindings/arm/marvell/ap806-system-controller.txt

Documentation/devicetree/bindings/arm/marvell/cp110-system-controller.txt



- reg: Device's register space.

  Two entries are expected, see the examples below. The first one points

  to the status register (4B). The second one points to the control

Documentation/devicetree/bindings/thermal/qcom-tsens.txt

+25 −6
Original line number Diff line number Diff line
@@ -2,17 +2,27 @@ 


Required properties:

- compatible:

 - "qcom,msm8916-tsens" : For 8916 Family of SoCs

 - "qcom,msm8974-tsens" : For 8974 Family of SoCs

 - "qcom,msm8996-tsens" : For 8996 Family of SoCs

  Must be one of the following:

    - "qcom,msm8916-tsens" (MSM8916)

    - "qcom,msm8974-tsens" (MSM8974)

    - "qcom,msm8996-tsens" (MSM8996)

    - "qcom,msm8998-tsens", "qcom,tsens-v2" (MSM8998)

    - "qcom,sdm845-tsens", "qcom,tsens-v2" (SDM845)

  The generic "qcom,tsens-v2" property must be used as a fallback for any SoC

  with version 2 of the TSENS IP. MSM8996 is the only exception because the

  generic property did not exist when support was added.



- reg: Address range of the thermal registers.

  New platforms containing v2.x.y of the TSENS IP must specify the SROT and TM

  register spaces separately, with order being TM before SROT.

  See Example 2, below.



- reg: Address range of the thermal registers

- #thermal-sensor-cells : Should be 1. See ./thermal.txt for a description.

- #qcom,sensors: Number of sensors in tsens block

- Refer to Documentation/devicetree/bindings/nvmem/nvmem.txt to know how to specify

nvmem cells



Example:

Example 1 (legacy support before a fallback tsens-v2 property was introduced):

tsens: thermal-sensor@900000 {

		compatible = "qcom,msm8916-tsens";

		reg = <0x4a8000 0x2000>;
@@ -20,3 +30,12 @@ tsens: thermal-sensor@900000 { 
		nvmem-cell-names = "caldata", "calsel";

		#thermal-sensor-cells = <1>;

	};



Example 2 (for any platform containing v2 of the TSENS IP):

tsens0: thermal-sensor@c263000 {

		compatible = "qcom,sdm845-tsens", "qcom,tsens-v2";

		reg = <0xc263000 0x1ff>, /* TM */

			<0xc222000 0x1ff>; /* SROT */

		#qcom,sensors = <13>;

		#thermal-sensor-cells = <1>;

	};

drivers/thermal/armada_thermal.c

+408 −126

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