Merge branch 'remotes/lorenzo/pci/mediatek'

#define AHB2PCIE_SIZE(x)	((x) & GENMASK(4, 0))

#define PCIE_AXI_WINDOW0	0x448

#define WIN_ENABLE		BIT(7)

/*

 * Define PCIe to AHB window size as 2^33 to support max 8GB address space

 * translate, support least 4GB DRAM size access from EP DMA(physical DRAM

 * start from 0x40000000).

 */

#define PCIE2AHB_SIZE	0x21

/* PCIe V2 configuration transaction header */

#define PCIE_CFG_HEADER0	0x460

	struct resource *mem = &pcie->mem;

	const struct mtk_pcie_soc *soc = port->pcie->soc;

	u32 val;

	size_t size;

	int err;

	/* MT7622 platforms need to enable LTSSM and ASPM from PCIe subsys */

		mtk_pcie_enable_msi(port);

	/* Set AHB to PCIe translation windows */

	size = mem->end - mem->start;

	val = lower_32_bits(mem->start) | AHB2PCIE_SIZE(fls(size));

	val = lower_32_bits(mem->start) |

	      AHB2PCIE_SIZE(fls(resource_size(mem)));

	writel(val, port->base + PCIE_AHB_TRANS_BASE0_L);

	val = upper_32_bits(mem->start);

	writel(val, port->base + PCIE_AHB_TRANS_BASE0_H);

	/* Set PCIe to AXI translation memory space.*/

	val = fls(0xffffffff) | WIN_ENABLE;

	val = PCIE2AHB_SIZE | WIN_ENABLE;

	writel(val, port->base + PCIE_AXI_WINDOW0);

	return 0;