Commit cfdcbcea authored by Gal Pressman's avatar Gal Pressman Committed by Saeed Mahameed
Browse files

net/mlx5: Expose PCAM, MCAM registers infrastructure 



PCAM: Ports capabilities mask register.
MCAM: Management capabilities mask register.

PCAM and MCAM registers will provide information regarding firmware
support for different features, in order to avoid cases where new driver
combined with old firmware results in syndromes (for ex. PCIe counters
before this patchset).

Signed-off-by: default avatarGal Pressman <galp@mellanox.com>
Signed-off-by: default avatarSaeed Mahameed <saeedm@mellanox.com>
parent 8a271746

include/linux/mlx5/device.h

+16 −0
Original line number Diff line number Diff line
@@ -970,6 +970,22 @@ enum mlx5_cap_type { 
	MLX5_CAP_NUM

};



enum mlx5_pcam_reg_groups {

	MLX5_PCAM_REGS_5000_TO_507F                 = 0x0,

};



enum mlx5_pcam_feature_groups {

	MLX5_PCAM_FEATURE_ENHANCED_FEATURES         = 0x0,

};



enum mlx5_mcam_reg_groups {

	MLX5_MCAM_REGS_FIRST_128                    = 0x0,

};



enum mlx5_mcam_feature_groups {

	MLX5_MCAM_FEATURE_ENHANCED_FEATURES         = 0x0,

};



/* GET Dev Caps macros */

#define MLX5_CAP_GEN(mdev, cap) \

	MLX5_GET(cmd_hca_cap, mdev->hca_caps_cur[MLX5_CAP_GENERAL], cap)

include/linux/mlx5/driver.h

+2 −0
Original line number Diff line number Diff line
@@ -121,12 +121,14 @@ enum { 
	MLX5_REG_PVLC		 = 0x500f,

	MLX5_REG_PCMR		 = 0x5041,

	MLX5_REG_PMLP		 = 0x5002,

	MLX5_REG_PCAM		 = 0x507f,

	MLX5_REG_NODE_DESC	 = 0x6001,

	MLX5_REG_HOST_ENDIANNESS = 0x7004,

	MLX5_REG_MCIA		 = 0x9014,

	MLX5_REG_MLCR		 = 0x902b,

	MLX5_REG_MTPPS		 = 0x9053,

	MLX5_REG_MTPPSE		 = 0x9054,

	MLX5_REG_MCAM		 = 0x907f,

};



enum mlx5_dcbx_oper_mode {

include/linux/mlx5/mlx5_ifc.h

+59 −1
Original line number Diff line number Diff line
@@ -826,7 +826,8 @@ struct mlx5_ifc_cmd_hca_cap_bits { 
	u8         nic_flow_table[0x1];

	u8         eswitch_flow_table[0x1];

	u8	   early_vf_enable[0x1];

	u8         reserved_at_1a9[0x2];

	u8         mcam_reg[0x1];

	u8         pcam_reg[0x1];

	u8         local_ca_ack_delay[0x5];

	u8         port_module_event[0x1];

	u8         reserved_at_1b1[0x1];
@@ -7481,6 +7482,63 @@ struct mlx5_ifc_peir_reg_bits { 
	u8         error_type[0x8];

};



struct mlx5_ifc_pcam_enhanced_features_bits {

	u8         reserved_at_0[0x7e];



	u8         ppcnt_discard_group[0x1];

	u8         ppcnt_statistical_group[0x1];

};



struct mlx5_ifc_pcam_reg_bits {

	u8         reserved_at_0[0x8];

	u8         feature_group[0x8];

	u8         reserved_at_10[0x8];

	u8         access_reg_group[0x8];



	u8         reserved_at_20[0x20];



	union {

		u8         reserved_at_0[0x80];

	} port_access_reg_cap_mask;



	u8         reserved_at_c0[0x80];



	union {

		struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features;

		u8         reserved_at_0[0x80];

	} feature_cap_mask;



	u8         reserved_at_1c0[0xc0];

};



struct mlx5_ifc_mcam_enhanced_features_bits {

	u8         reserved_at_0[0x7f];



	u8         pcie_performance_group[0x1];

};



struct mlx5_ifc_mcam_reg_bits {

	u8         reserved_at_0[0x8];

	u8         feature_group[0x8];

	u8         reserved_at_10[0x8];

	u8         access_reg_group[0x8];



	u8         reserved_at_20[0x20];



	union {

		u8         reserved_at_0[0x80];

	} mng_access_reg_cap_mask;



	u8         reserved_at_c0[0x80];



	union {

		struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features;

		u8         reserved_at_0[0x80];

	} mng_feature_cap_mask;



	u8         reserved_at_1c0[0x80];

};



struct mlx5_ifc_pcap_reg_bits {

	u8         reserved_at_0[0x8];

	u8         local_port[0x8];

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