Commit cfda8617 authored by Yash Shah's avatar Yash Shah Committed by Paul Walmsley
Browse files

riscv: dts: Add DT support for SiFive L2 cache controller 



Add the L2 cache controller DT node in SiFive FU540 soc-specific DT file

Signed-off-by: default avatarYash Shah <yash.shah@sifive.com>
Reviewed-by: default avatarPalmer Dabbelt <palmerdabbelt@google.com>
Signed-off-by: default avatarPaul Walmsley <paul.walmsley@sifive.com>
parent 0da310e8

arch/riscv/boot/dts/sifive/fu540-c000.dtsi

+15 −0
Original line number Diff line number Diff line
@@ -54,6 +54,7 @@ 
			reg = <1>;

			riscv,isa = "rv64imafdc";

			tlb-split;

			next-level-cache = <&l2cache>;

			cpu1_intc: interrupt-controller {

				#interrupt-cells = <1>;

				compatible = "riscv,cpu-intc";
@@ -77,6 +78,7 @@ 
			reg = <2>;

			riscv,isa = "rv64imafdc";

			tlb-split;

			next-level-cache = <&l2cache>;

			cpu2_intc: interrupt-controller {

				#interrupt-cells = <1>;

				compatible = "riscv,cpu-intc";
@@ -100,6 +102,7 @@ 
			reg = <3>;

			riscv,isa = "rv64imafdc";

			tlb-split;

			next-level-cache = <&l2cache>;

			cpu3_intc: interrupt-controller {

				#interrupt-cells = <1>;

				compatible = "riscv,cpu-intc";
@@ -123,6 +126,7 @@ 
			reg = <4>;

			riscv,isa = "rv64imafdc";

			tlb-split;

			next-level-cache = <&l2cache>;

			cpu4_intc: interrupt-controller {

				#interrupt-cells = <1>;

				compatible = "riscv,cpu-intc";
@@ -253,6 +257,17 @@ 
			#pwm-cells = <3>;

			status = "disabled";

		};

		l2cache: cache-controller@2010000 {

			compatible = "sifive,fu540-c000-ccache", "cache";

			cache-block-size = <64>;

			cache-level = <2>;

			cache-sets = <1024>;

			cache-size = <2097152>;

			cache-unified;

			interrupt-parent = <&plic0>;

			interrupts = <1 2 3>;

			reg = <0x0 0x2010000 0x0 0x1000>;

		};



	};

};

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