Commit cfd1c488 authored by Chris Wilson's avatar Chris Wilson
Browse files

drm/i915: Move the common RPS warnings to intel_set_rps() 



Instead of having each back-end provide identical guards, just have a
singular set in intel_set_rps() to verify that the caller is obeying the
rules.

Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: default avatarRadoslaw Szwichtenberg <radoslaw.szwichtenberg@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/20170220094713.22874-1-chris@chris-wilson.co.uk
parent 784f2f1a

drivers/gpu/drm/i915/intel_pm.c

+4 −8
Original line number Diff line number Diff line
@@ -4914,10 +4914,6 @@ static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val) 
 * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */

static int gen6_set_rps(struct drm_i915_private *dev_priv, u8 val)

{

	WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));

	WARN_ON(val > dev_priv->rps.max_freq);

	WARN_ON(val < dev_priv->rps.min_freq);



	/* min/max delay may still have been modified so be sure to

	 * write the limits value.

	 */
@@ -4955,10 +4951,6 @@ static int valleyview_set_rps(struct drm_i915_private *dev_priv, u8 val) 
{

	int err;



	WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));

	WARN_ON(val > dev_priv->rps.max_freq);

	WARN_ON(val < dev_priv->rps.min_freq);



	if (WARN_ONCE(IS_CHERRYVIEW(dev_priv) && (val & 1),

		      "Odd GPU freq value\n"))

		val &= ~1;
@@ -5109,6 +5101,10 @@ int intel_set_rps(struct drm_i915_private *dev_priv, u8 val) 
{

	int err;



	lockdep_assert_held(&dev_priv->rps.hw_lock);

	GEM_BUG_ON(val > dev_priv->rps.max_freq);

	GEM_BUG_ON(val < dev_priv->rps.min_freq);



	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))

		err = valleyview_set_rps(dev_priv, val);

	else

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