Commit cfd12db4 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'spi-v4.18' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi 

Pull spi updates from Mark Brown:
 "Quite a busy release for SPI, mainly as a result of Boris Brezillon's
  work on improving the integration with MTD for accelerated SPI flash
  controllers. He's added a new spi_mem interface which works a lot
  better with general hardware and converted the users over to it, as a
  result of this work we've got some MTD changes in here as well.

  Other highlights include:

   - Lots of spring cleaning for the s3c64xx driver.

   - Removal of the bcm53xx, the hardware is also supported by the mspi
     driver but SoC naming had caused people to miss the duplication.

   - Conversion of the pxa2xx driver to use the standard message
     processing loop rather than open coding.

   - A bunch of improvements to the runtime PM of the OMAP McSPI driver"

* tag 'spi-v4.18' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi: (47 commits)
  spi: Fix typo on SPI_MEM help text
  spi: sh-msiof: Fix setting SIRMDR1.SYNCAC to match SITMDR1.SYNCAC
  mtd: devices: m25p80: Use spi_mem_set_drvdata() instead of spi_set_drvdata()
  spi: omap2-mcspi: Remove unnecessary pm_runtime_force_suspend()
  spi: Add missing pm_runtime_put_noidle() after failed get
  spi: ti-qspi: Make sure res_mmap != NULL before dereferencing it
  spi: spi-s3c64xx: Fix system resume support
  spi: bcm-qspi: Fix build failure caused by spi_flash_read() API removal
  spi: Get rid of the spi_flash_read() API
  mtd: spi-nor: Use the spi_mem_xx() API
  spi: ti-qspi: Implement the spi_mem interface
  spi: bcm-qspi: Implement the spi_mem interface
  spi: Make support for regular transfers optional when ->mem_ops != NULL
  spi: Extend the core to ease integration of SPI memory controllers
  spi: remove forgotten CONFIG_SPI_BCM53XX
  spi: remove the older/duplicated bcm53xx driver
  spi: pxa2xx: check clk_prepare_enable() return value
  spi: lpspi: Switch to SPDX identifier
  spi: mxs: Switch to SPDX identifier
  spi: imx: Switch to SPDX identifier
  ...
parents 910470e0 16c10b3b

drivers/mtd/devices/Kconfig

+1 −0
Original line number Diff line number Diff line
@@ -81,6 +81,7 @@ config MTD_DATAFLASH_OTP 
config MTD_M25P80

	tristate "Support most SPI Flash chips (AT26DF, M25P, W25X, ...)"

	depends on SPI_MASTER && MTD_SPI_NOR

	select SPI_MEM

	help

	  This enables access to most modern SPI flash chips, used for

	  program and data storage.   Series supported include Atmel AT26DF,

drivers/mtd/devices/m25p80.c

+80 −158
Original line number Diff line number Diff line
@@ -24,12 +24,13 @@ 
#include <linux/mtd/partitions.h>



#include <linux/spi/spi.h>

#include <linux/spi/spi-mem.h>

#include <linux/spi/flash.h>

#include <linux/mtd/spi-nor.h>



#define	MAX_CMD_SIZE		6

struct m25p {

	struct spi_device	*spi;

	struct spi_mem		*spimem;

	struct spi_nor		spi_nor;

	u8			command[MAX_CMD_SIZE];

};
@@ -37,97 +38,68 @@ struct m25p { 
static int m25p80_read_reg(struct spi_nor *nor, u8 code, u8 *val, int len)

{

	struct m25p *flash = nor->priv;

	struct spi_device *spi = flash->spi;

	struct spi_mem_op op = SPI_MEM_OP(SPI_MEM_OP_CMD(code, 1),

					  SPI_MEM_OP_NO_ADDR,

					  SPI_MEM_OP_NO_DUMMY,

					  SPI_MEM_OP_DATA_IN(len, val, 1));

	int ret;



	ret = spi_write_then_read(spi, &code, 1, val, len);

	ret = spi_mem_exec_op(flash->spimem, &op);

	if (ret < 0)

		dev_err(&spi->dev, "error %d reading %x\n", ret, code);

		dev_err(&flash->spimem->spi->dev, "error %d reading %x\n", ret,

			code);



	return ret;

}



static void m25p_addr2cmd(struct spi_nor *nor, unsigned int addr, u8 *cmd)

{

	/* opcode is in cmd[0] */

	cmd[1] = addr >> (nor->addr_width * 8 -  8);

	cmd[2] = addr >> (nor->addr_width * 8 - 16);

	cmd[3] = addr >> (nor->addr_width * 8 - 24);

	cmd[4] = addr >> (nor->addr_width * 8 - 32);

}



static int m25p_cmdsz(struct spi_nor *nor)

{

	return 1 + nor->addr_width;

}



static int m25p80_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)

{

	struct m25p *flash = nor->priv;

	struct spi_device *spi = flash->spi;

	struct spi_mem_op op = SPI_MEM_OP(SPI_MEM_OP_CMD(opcode, 1),

					  SPI_MEM_OP_NO_ADDR,

					  SPI_MEM_OP_NO_DUMMY,

					  SPI_MEM_OP_DATA_OUT(len, buf, 1));



	flash->command[0] = opcode;

	if (buf)

		memcpy(&flash->command[1], buf, len);



	return spi_write(spi, flash->command, len + 1);

	return spi_mem_exec_op(flash->spimem, &op);

}



static ssize_t m25p80_write(struct spi_nor *nor, loff_t to, size_t len,

			    const u_char *buf)

{

	struct m25p *flash = nor->priv;

	struct spi_device *spi = flash->spi;

	unsigned int inst_nbits, addr_nbits, data_nbits, data_idx;

	struct spi_transfer t[3] = {};

	struct spi_message m;

	int cmd_sz = m25p_cmdsz(nor);

	ssize_t ret;

	struct spi_mem_op op =

			SPI_MEM_OP(SPI_MEM_OP_CMD(nor->program_opcode, 1),

				   SPI_MEM_OP_ADDR(nor->addr_width, to, 1),

				   SPI_MEM_OP_DUMMY(0, 1),

				   SPI_MEM_OP_DATA_OUT(len, buf, 1));

	size_t remaining = len;

	int ret;



	/* get transfer protocols. */

	inst_nbits = spi_nor_get_protocol_inst_nbits(nor->write_proto);

	addr_nbits = spi_nor_get_protocol_addr_nbits(nor->write_proto);

	data_nbits = spi_nor_get_protocol_data_nbits(nor->write_proto);



	spi_message_init(&m);

	op.cmd.buswidth = spi_nor_get_protocol_inst_nbits(nor->write_proto);

	op.addr.buswidth = spi_nor_get_protocol_addr_nbits(nor->write_proto);

	op.dummy.buswidth = op.addr.buswidth;

	op.data.buswidth = spi_nor_get_protocol_data_nbits(nor->write_proto);



	if (nor->program_opcode == SPINOR_OP_AAI_WP && nor->sst_write_second)

		cmd_sz = 1;



	flash->command[0] = nor->program_opcode;

	m25p_addr2cmd(nor, to, flash->command);



	t[0].tx_buf = flash->command;

	t[0].tx_nbits = inst_nbits;

	t[0].len = cmd_sz;

	spi_message_add_tail(&t[0], &m);

		op.addr.nbytes = 0;



	/* split the op code and address bytes into two transfers if needed. */

	data_idx = 1;

	if (addr_nbits != inst_nbits) {

		t[0].len = 1;



		t[1].tx_buf = &flash->command[1];

		t[1].tx_nbits = addr_nbits;

		t[1].len = cmd_sz - 1;

		spi_message_add_tail(&t[1], &m);



		data_idx = 2;

	}



	t[data_idx].tx_buf = buf;

	t[data_idx].tx_nbits = data_nbits;

	t[data_idx].len = len;

	spi_message_add_tail(&t[data_idx], &m);



	ret = spi_sync(spi, &m);

	while (remaining) {

		op.data.nbytes = remaining < UINT_MAX ? remaining : UINT_MAX;

		ret = spi_mem_adjust_op_size(flash->spimem, &op);

		if (ret)

			return ret;



	ret = m.actual_length - cmd_sz;

	if (ret < 0)

		return -EIO;

		ret = spi_mem_exec_op(flash->spimem, &op);

		if (ret)

			return ret;



		op.addr.val += op.data.nbytes;

		remaining -= op.data.nbytes;

		op.data.buf.out += op.data.nbytes;

	}



	return len;

}



/*
@@ -138,92 +110,39 @@ static ssize_t m25p80_read(struct spi_nor *nor, loff_t from, size_t len, 
			   u_char *buf)

{

	struct m25p *flash = nor->priv;

	struct spi_device *spi = flash->spi;

	unsigned int inst_nbits, addr_nbits, data_nbits, data_idx;

	struct spi_transfer t[3];

	struct spi_message m;

	unsigned int dummy = nor->read_dummy;

	ssize_t ret;

	int cmd_sz;

	struct spi_mem_op op =

			SPI_MEM_OP(SPI_MEM_OP_CMD(nor->read_opcode, 1),

				   SPI_MEM_OP_ADDR(nor->addr_width, from, 1),

				   SPI_MEM_OP_DUMMY(nor->read_dummy, 1),

				   SPI_MEM_OP_DATA_IN(len, buf, 1));

	size_t remaining = len;

	int ret;



	/* get transfer protocols. */

	inst_nbits = spi_nor_get_protocol_inst_nbits(nor->read_proto);

	addr_nbits = spi_nor_get_protocol_addr_nbits(nor->read_proto);

	data_nbits = spi_nor_get_protocol_data_nbits(nor->read_proto);

	op.cmd.buswidth = spi_nor_get_protocol_inst_nbits(nor->read_proto);

	op.addr.buswidth = spi_nor_get_protocol_addr_nbits(nor->read_proto);

	op.dummy.buswidth = op.addr.buswidth;

	op.data.buswidth = spi_nor_get_protocol_data_nbits(nor->read_proto);



	/* convert the dummy cycles to the number of bytes */

	dummy = (dummy * addr_nbits) / 8;

	op.dummy.nbytes = (nor->read_dummy * op.dummy.buswidth) / 8;



	if (spi_flash_read_supported(spi)) {

		struct spi_flash_read_message msg;



		memset(&msg, 0, sizeof(msg));



		msg.buf = buf;

		msg.from = from;

		msg.len = len;

		msg.read_opcode = nor->read_opcode;

		msg.addr_width = nor->addr_width;

		msg.dummy_bytes = dummy;

		msg.opcode_nbits = inst_nbits;

		msg.addr_nbits = addr_nbits;

		msg.data_nbits = data_nbits;



		ret = spi_flash_read(spi, &msg);

		if (ret < 0)

	while (remaining) {

		op.data.nbytes = remaining < UINT_MAX ? remaining : UINT_MAX;

		ret = spi_mem_adjust_op_size(flash->spimem, &op);

		if (ret)

			return ret;

		return msg.retlen;

	}



	spi_message_init(&m);

	memset(t, 0, (sizeof t));



	flash->command[0] = nor->read_opcode;

	m25p_addr2cmd(nor, from, flash->command);



	t[0].tx_buf = flash->command;

	t[0].tx_nbits = inst_nbits;

	t[0].len = m25p_cmdsz(nor) + dummy;

	spi_message_add_tail(&t[0], &m);



	/*

	 * Set all dummy/mode cycle bits to avoid sending some manufacturer

	 * specific pattern, which might make the memory enter its Continuous

	 * Read mode by mistake.

	 * Based on the different mode cycle bit patterns listed and described

	 * in the JESD216B specification, the 0xff value works for all memories

	 * and all manufacturers.

	 */

	cmd_sz = t[0].len;

	memset(flash->command + cmd_sz - dummy, 0xff, dummy);



	/* split the op code and address bytes into two transfers if needed. */

	data_idx = 1;

	if (addr_nbits != inst_nbits) {

		t[0].len = 1;



		t[1].tx_buf = &flash->command[1];

		t[1].tx_nbits = addr_nbits;

		t[1].len = cmd_sz - 1;

		spi_message_add_tail(&t[1], &m);



		data_idx = 2;

	}



	t[data_idx].rx_buf = buf;

	t[data_idx].rx_nbits = data_nbits;

	t[data_idx].len = min3(len, spi_max_transfer_size(spi),

			       spi_max_message_size(spi) - cmd_sz);

	spi_message_add_tail(&t[data_idx], &m);



	ret = spi_sync(spi, &m);

		ret = spi_mem_exec_op(flash->spimem, &op);

		if (ret)

			return ret;



	ret = m.actual_length - cmd_sz;

	if (ret < 0)

		return -EIO;

	return ret;

		op.addr.val += op.data.nbytes;

		remaining -= op.data.nbytes;

		op.data.buf.in += op.data.nbytes;

	}



	return len;

}



/*
@@ -231,8 +150,9 @@ static ssize_t m25p80_read(struct spi_nor *nor, loff_t from, size_t len, 
 * matches what the READ command supports, at least until this driver

 * understands FAST_READ (for clocks over 25 MHz).

 */

static int m25p_probe(struct spi_device *spi)

static int m25p_probe(struct spi_mem *spimem)

{

	struct spi_device *spi = spimem->spi;

	struct flash_platform_data	*data;

	struct m25p *flash;

	struct spi_nor *nor;
@@ -244,9 +164,9 @@ static int m25p_probe(struct spi_device *spi) 
	char *flash_name;

	int ret;



	data = dev_get_platdata(&spi->dev);

	data = dev_get_platdata(&spimem->spi->dev);



	flash = devm_kzalloc(&spi->dev, sizeof(*flash), GFP_KERNEL);

	flash = devm_kzalloc(&spimem->spi->dev, sizeof(*flash), GFP_KERNEL);

	if (!flash)

		return -ENOMEM;
@@ -258,12 +178,12 @@ static int m25p_probe(struct spi_device *spi) 
	nor->write_reg = m25p80_write_reg;

	nor->read_reg = m25p80_read_reg;



	nor->dev = &spi->dev;

	nor->dev = &spimem->spi->dev;

	spi_nor_set_flash_node(nor, spi->dev.of_node);

	nor->priv = flash;



	spi_set_drvdata(spi, flash);

	flash->spi = spi;

	spi_mem_set_drvdata(spimem, flash);

	flash->spimem = spimem;



	if (spi->mode & SPI_RX_QUAD) {

		hwcaps.mask |= SNOR_HWCAPS_READ_1_1_4;
@@ -303,9 +223,9 @@ static int m25p_probe(struct spi_device *spi) 
}





static int m25p_remove(struct spi_device *spi)

static int m25p_remove(struct spi_mem *spimem)

{

	struct m25p	*flash = spi_get_drvdata(spi);

	struct m25p	*flash = spi_mem_get_drvdata(spimem);



	spi_nor_restore(&flash->spi_nor);
@@ -313,9 +233,9 @@ static int m25p_remove(struct spi_device *spi) 
	return mtd_device_unregister(&flash->spi_nor.mtd);

}



static void m25p_shutdown(struct spi_device *spi)

static void m25p_shutdown(struct spi_mem *spimem)

{

	struct m25p *flash = spi_get_drvdata(spi);

	struct m25p *flash = spi_mem_get_drvdata(spimem);



	spi_nor_restore(&flash->spi_nor);

}
@@ -386,12 +306,14 @@ static const struct of_device_id m25p_of_table[] = { 
};

MODULE_DEVICE_TABLE(of, m25p_of_table);



static struct spi_driver m25p80_driver = {

static struct spi_mem_driver m25p80_driver = {

	.spidrv = {

		.driver = {

			.name	= "m25p80",

			.of_match_table = m25p_of_table,

		},

		.id_table	= m25p_ids,

	},

	.probe	= m25p_probe,

	.remove	= m25p_remove,

	.shutdown	= m25p_shutdown,
@@ -402,7 +324,7 @@ static struct spi_driver m25p80_driver = { 
	 */

};



module_spi_driver(m25p80_driver);

module_spi_mem_driver(m25p80_driver);



MODULE_LICENSE("GPL");

MODULE_AUTHOR("Mike Lavender");

drivers/spi/Kconfig

+10 −17
Original line number Diff line number Diff line
@@ -47,6 +47,13 @@ config SPI_MASTER 


if SPI_MASTER



config SPI_MEM

	bool "SPI memory extension"

	help

	  Enable this option if you want to enable the SPI memory extension.

	  This extension is meant to simplify interaction with SPI memories

	  by providing a high-level interface to send memory-like commands.



comment "SPI Master Controller Drivers"



config SPI_ALTERA
@@ -71,7 +78,6 @@ config SPI_ARMADA_3700 


config SPI_ATMEL

	tristate "Atmel SPI Controller"

	depends on HAS_DMA

	depends on ARCH_AT91 || COMPILE_TEST

	help

	  This selects a driver for the Atmel SPI Controller, present on
@@ -115,14 +121,6 @@ config SPI_BCM2835AUX 
	  "universal SPI master", and the regular SPI controller.

	  This driver is for the universal/auxiliary SPI controller.



config SPI_BCM53XX

	tristate "Broadcom BCM53xx SPI controller"

	depends on ARCH_BCM_5301X

	depends on BCMA_POSSIBLE

	select BCMA

	help

          Enable support for the SPI controller on Broadcom BCM53xx ARM SoCs.



config SPI_BCM63XX

	tristate "Broadcom BCM63xx SPI controller"

	depends on BCM63XX || COMPILE_TEST
@@ -233,7 +231,6 @@ config SPI_EFM32 


config SPI_EP93XX

	tristate "Cirrus Logic EP93xx SPI controller"

	depends on HAS_DMA

	depends on ARCH_EP93XX || COMPILE_TEST

	help

	  This enables using the Cirrus EP93xx SPI controller in master
@@ -355,7 +352,6 @@ config SPI_FSL_SPI 
config SPI_FSL_DSPI

	tristate "Freescale DSPI controller"

	select REGMAP_MMIO

	depends on HAS_DMA

	depends on SOC_VF610 || SOC_LS1021A || ARCH_LAYERSCAPE || M5441x || COMPILE_TEST

	help

	  This enables support for the Freescale DSPI controller in master
@@ -431,7 +427,6 @@ config SPI_OMAP_UWIRE 


config SPI_OMAP24XX

	tristate "McSPI driver for OMAP"

	depends on HAS_DMA

	depends on ARCH_OMAP2PLUS || COMPILE_TEST

	select SG_SPLIT

	help
@@ -440,7 +435,6 @@ config SPI_OMAP24XX 


config SPI_TI_QSPI

	tristate "DRA7xxx QSPI controller support"

	depends on HAS_DMA

	depends on ARCH_OMAP2PLUS || COMPILE_TEST

	help

	  QSPI master controller for DRA7xxx used for flash devices.
@@ -469,7 +463,6 @@ config SPI_PIC32 
config SPI_PIC32_SQI

	tristate "Microchip PIC32 Quad SPI driver"

	depends on MACH_PIC32 || COMPILE_TEST

	depends on HAS_DMA

	help

	  SPI driver for PIC32 Quad SPI controller.
@@ -572,7 +565,7 @@ config SPI_SC18IS602 


config SPI_SH_MSIOF

	tristate "SuperH MSIOF SPI controller"

	depends on HAVE_CLK && HAS_DMA

	depends on HAVE_CLK

	depends on ARCH_SHMOBILE || ARCH_RENESAS || COMPILE_TEST

	help

	  SPI driver for SuperH and SH Mobile MSIOF blocks.
@@ -650,7 +643,7 @@ config SPI_MXS 
config SPI_TEGRA114

	tristate "NVIDIA Tegra114 SPI Controller"

	depends on (ARCH_TEGRA && TEGRA20_APB_DMA) || COMPILE_TEST

	depends on RESET_CONTROLLER && HAS_DMA

	depends on RESET_CONTROLLER

	help

	  SPI driver for NVIDIA Tegra114 SPI Controller interface. This controller

	  is different than the older SoCs SPI controller and also register interface
@@ -668,7 +661,7 @@ config SPI_TEGRA20_SFLASH 
config SPI_TEGRA20_SLINK

	tristate "Nvidia Tegra20/Tegra30 SLINK Controller"

	depends on (ARCH_TEGRA && TEGRA20_APB_DMA) || COMPILE_TEST

	depends on RESET_CONTROLLER && HAS_DMA

	depends on RESET_CONTROLLER

	help

	  SPI driver for Nvidia Tegra20/Tegra30 SLINK Controller interface.

drivers/spi/Makefile

+1 −1
Original line number Diff line number Diff line
@@ -8,6 +8,7 @@ ccflags-$(CONFIG_SPI_DEBUG) := -DDEBUG 
# small core, mostly translating board-specific

# config declarations into driver model code

obj-$(CONFIG_SPI_MASTER)		+= spi.o

obj-$(CONFIG_SPI_MEM)			+= spi-mem.o

obj-$(CONFIG_SPI_SPIDEV)		+= spidev.o

obj-$(CONFIG_SPI_LOOPBACK_TEST)		+= spi-loopback-test.o
@@ -20,7 +21,6 @@ obj-$(CONFIG_SPI_AU1550) += spi-au1550.o 
obj-$(CONFIG_SPI_AXI_SPI_ENGINE)	+= spi-axi-spi-engine.o

obj-$(CONFIG_SPI_BCM2835)		+= spi-bcm2835.o

obj-$(CONFIG_SPI_BCM2835AUX)		+= spi-bcm2835aux.o

obj-$(CONFIG_SPI_BCM53XX)		+= spi-bcm53xx.o

obj-$(CONFIG_SPI_BCM63XX)		+= spi-bcm63xx.o

obj-$(CONFIG_SPI_BCM63XX_HSSPI)		+= spi-bcm63xx-hsspi.o

obj-$(CONFIG_SPI_BCM_QSPI)		+= spi-iproc-qspi.o spi-brcmstb-qspi.o spi-bcm-qspi.o

drivers/spi/internals.h

0 → 100644
+43 −0
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0+ */

/*

 * Copyright (C) 2018 Exceet Electronics GmbH

 * Copyright (C) 2018 Bootlin

 *

 * Author: Boris Brezillon <boris.brezillon@bootlin.com>

 *

 * Helpers needed by the spi or spi-mem logic. Should not be used outside of

 * spi-mem.c and spi.c.

 */



#ifndef __LINUX_SPI_INTERNALS_H

#define __LINUX_SPI_INTERNALS_H



#include <linux/device.h>

#include <linux/dma-direction.h>

#include <linux/scatterlist.h>

#include <linux/spi/spi.h>



void spi_flush_queue(struct spi_controller *ctrl);



#ifdef CONFIG_HAS_DMA

int spi_map_buf(struct spi_controller *ctlr, struct device *dev,

		struct sg_table *sgt, void *buf, size_t len,

		enum dma_data_direction dir);

void spi_unmap_buf(struct spi_controller *ctlr, struct device *dev,

		   struct sg_table *sgt, enum dma_data_direction dir);

#else /* !CONFIG_HAS_DMA */

static inline int spi_map_buf(struct spi_controller *ctlr, struct device *dev,

			      struct sg_table *sgt, void *buf, size_t len,

			      enum dma_data_direction dir)

{

	return -EINVAL;

}



static inline void spi_unmap_buf(struct spi_controller *ctlr,

				 struct device *dev, struct sg_table *sgt,

				 enum dma_data_direction dir)

{

}

#endif /* CONFIG_HAS_DMA */



#endif /* __LINUX_SPI_INTERNALS_H */

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