Commit cf9d2890 authored by Yu Zhang's avatar Yu Zhang Committed by Daniel Vetter
Browse files

drm/i915: Introduce a PV INFO page structure for Intel GVT-g. 



Introduce a PV INFO structure, to facilitate the Intel GVT-g
technology, which is a GPU virtualization solution with mediated
pass-through. This page contains the shared information between
i915 driver and the host emulator. For now, this structure utilizes
an area of 4K bytes on HSW GPU's unused MMIO space. Future hardware
will have the reserved window architecturally defined, and layout
of the page will be added in future BSpec.

The i915 driver load routine detects if it is running in a VM by
reading the contents of this PV INFO page. Thereafter a flag,
vgpu.active is set, and intel_vgpu_active() is used by checking
this flag to conclude if GPU is virtualized with Intel GVT-g. By
now, intel_vgpu_active() will return true, only when the driver
is running as a guest in the Intel GVT-g enhanced environment on
HSW platform.

v2:
take Chris' comments:
        - call the i915_check_vgpu() in intel_uncore_init()
        - sanitize i915_check_vgpu() by adding BUILD_BUG_ON() and debug info
take Daniel's comments:
        - put the definition of PV INFO into a new header - i915_vgt_if.h
other changes:
        - access mmio regs by readq/readw in i915_check_vgpu()

v3:
take Daniel's comments:
        - move the i915/vgt interfaces into a new i915_vgpu.c
        - update makefile
        - add kerneldoc to functions which are non-static
        - add a DOC: section describing some of the high-level design
        - update drm docbook
other changes:
        - rename i915_vgt_if.h to i915_vgpu.h

v4:
take Tvrtko's comments:
        - fix a typo in commit message
        - add debug message when vgt version mismatches
        - rename low_gmadr/high_gmadr to mappable/non-mappable in PV INFO
          structure

Signed-off-by: default avatarYu Zhang <yu.c.zhang@linux.intel.com>
Signed-off-by: default avatarJike Song <jike.song@intel.com>
Signed-off-by: default avatarEddie Dong <eddie.dong@intel.com>
Reviewed-by: default avatarTvrtko Ursulin <tvrtko.ursulin@intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 5baa22c5

Documentation/DocBook/drm.tmpl

+5 −0
Original line number Diff line number Diff line
@@ -3979,6 +3979,11 @@ int num_ioctls;</synopsis> 
!Fdrivers/gpu/drm/i915/i915_irq.c intel_runtime_pm_disable_interrupts

!Fdrivers/gpu/drm/i915/i915_irq.c intel_runtime_pm_enable_interrupts

      </sect2>

      <sect2>

        <title>Intel GVT-g Guest Support(vGPU)</title>

!Pdrivers/gpu/drm/i915/i915_vgpu.c Intel GVT-g guest support

!Idrivers/gpu/drm/i915/i915_vgpu.c

      </sect2>

    </sect1>

    <sect1>

      <title>Display Hardware Handling</title>

drivers/gpu/drm/i915/Makefile

+3 −0
Original line number Diff line number Diff line
@@ -83,6 +83,9 @@ i915-y += dvo_ch7017.o \ 
	  intel_sdvo.o \

	  intel_tv.o



# virtual gpu code

i915-y += i915_vgpu.o



# legacy horrors

i915-y += i915_dma.o \

	  i915_ums.o

drivers/gpu/drm/i915/i915_drv.h

+10 −0
Original line number Diff line number Diff line
@@ -1641,6 +1641,10 @@ struct i915_workarounds { 
	u32 count;

};



struct i915_virtual_gpu {

	bool active;

};



struct drm_i915_private {

	struct drm_device *dev;

	struct kmem_cache *slab;
@@ -1653,6 +1657,8 @@ struct drm_i915_private { 


	struct intel_uncore uncore;



	struct i915_virtual_gpu vgpu;



	struct intel_gmbus gmbus[GMBUS_NUM_PORTS];
@@ -2585,6 +2591,10 @@ void intel_uncore_forcewake_get(struct drm_i915_private *dev_priv, 
void intel_uncore_forcewake_put(struct drm_i915_private *dev_priv,

				enum forcewake_domains domains);

void assert_forcewakes_inactive(struct drm_i915_private *dev_priv);

static inline bool intel_vgpu_active(struct drm_device *dev)

{

	return to_i915(dev)->vgpu.active;

}



void

i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,

drivers/gpu/drm/i915/i915_vgpu.c

0 → 100644
+86 −0
Original line number Diff line number Diff line 
/*

 * Copyright(c) 2011-2015 Intel Corporation. All rights reserved.

 *

 * Permission is hereby granted, free of charge, to any person obtaining a

 * copy of this software and associated documentation files (the "Software"),

 * to deal in the Software without restriction, including without limitation

 * the rights to use, copy, modify, merge, publish, distribute, sublicense,

 * and/or sell copies of the Software, and to permit persons to whom the

 * Software is furnished to do so, subject to the following conditions:

 *

 * The above copyright notice and this permission notice (including the next

 * paragraph) shall be included in all copies or substantial portions of the

 * Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL

 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER

 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,

 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE

 * SOFTWARE.

 */



#include "intel_drv.h"

#include "i915_vgpu.h"



/**

 * DOC: Intel GVT-g guest support

 *

 * Intel GVT-g is a graphics virtualization technology which shares the

 * GPU among multiple virtual machines on a time-sharing basis. Each

 * virtual machine is presented a virtual GPU (vGPU), which has equivalent

 * features as the underlying physical GPU (pGPU), so i915 driver can run

 * seamlessly in a virtual machine. This file provides vGPU specific

 * optimizations when running in a virtual machine, to reduce the complexity

 * of vGPU emulation and to improve the overall performance.

 *

 * A primary function introduced here is so-called "address space ballooning"

 * technique. Intel GVT-g partitions global graphics memory among multiple VMs,

 * so each VM can directly access a portion of the memory without hypervisor's

 * intervention, e.g. filling textures or queuing commands. However with the

 * partitioning an unmodified i915 driver would assume a smaller graphics

 * memory starting from address ZERO, then requires vGPU emulation module to

 * translate the graphics address between 'guest view' and 'host view', for

 * all registers and command opcodes which contain a graphics memory address.

 * To reduce the complexity, Intel GVT-g introduces "address space ballooning",

 * by telling the exact partitioning knowledge to each guest i915 driver, which

 * then reserves and prevents non-allocated portions from allocation. Thus vGPU

 * emulation module only needs to scan and validate graphics addresses without

 * complexity of address translation.

 *

 */



/**

 * i915_check_vgpu - detect virtual GPU

 * @dev: drm device *

 *

 * This function is called at the initialization stage, to detect whether

 * running on a vGPU.

 */

void i915_check_vgpu(struct drm_device *dev)

{

	struct drm_i915_private *dev_priv = to_i915(dev);

	uint64_t magic;

	uint32_t version;



	BUILD_BUG_ON(sizeof(struct vgt_if) != VGT_PVINFO_SIZE);



	if (!IS_HASWELL(dev))

		return;



	magic = readq(dev_priv->regs + vgtif_reg(magic));

	if (magic != VGT_MAGIC)

		return;



	version = INTEL_VGT_IF_VERSION_ENCODE(

		readw(dev_priv->regs + vgtif_reg(version_major)),

		readw(dev_priv->regs + vgtif_reg(version_minor)));

	if (version != INTEL_VGT_IF_VERSION) {

		DRM_INFO("VGT interface version mismatch!\n");

		return;

	}



	dev_priv->vgpu.active = true;

	DRM_INFO("Virtual GPU for Intel GVT-g detected.\n");

}

drivers/gpu/drm/i915/i915_vgpu.h

0 → 100644
+85 −0
Original line number Diff line number Diff line 
/*

 * Copyright(c) 2011-2015 Intel Corporation. All rights reserved.

 *

 * Permission is hereby granted, free of charge, to any person obtaining a

 * copy of this software and associated documentation files (the "Software"),

 * to deal in the Software without restriction, including without limitation

 * the rights to use, copy, modify, merge, publish, distribute, sublicense,

 * and/or sell copies of the Software, and to permit persons to whom the

 * Software is furnished to do so, subject to the following conditions:

 *

 * The above copyright notice and this permission notice (including the next

 * paragraph) shall be included in all copies or substantial portions of the

 * Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL

 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER

 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,

 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE

 * SOFTWARE.

 */



#ifndef _I915_VGPU_H_

#define _I915_VGPU_H_



/* The MMIO offset of the shared info between guest and host emulator */

#define VGT_PVINFO_PAGE	0x78000

#define VGT_PVINFO_SIZE	0x1000



/*

 * The following structure pages are defined in GEN MMIO space

 * for virtualization. (One page for now)

 */

#define VGT_MAGIC         0x4776544776544776	/* 'vGTvGTvG' */

#define VGT_VERSION_MAJOR 1

#define VGT_VERSION_MINOR 0



#define INTEL_VGT_IF_VERSION_ENCODE(major, minor) ((major) << 16 | (minor))

#define INTEL_VGT_IF_VERSION \

	INTEL_VGT_IF_VERSION_ENCODE(VGT_VERSION_MAJOR, VGT_VERSION_MINOR)



struct vgt_if {

	uint64_t magic;		/* VGT_MAGIC */

	uint16_t version_major;

	uint16_t version_minor;

	uint32_t vgt_id;	/* ID of vGT instance */

	uint32_t rsv1[12];	/* pad to offset 0x40 */

	/*

	 *  Data structure to describe the balooning info of resources.

	 *  Each VM can only have one portion of continuous area for now.

	 *  (May support scattered resource in future)

	 *  (starting from offset 0x40)

	 */

	struct {

		/* Aperture register balooning */

		struct {

			uint32_t base;

			uint32_t size;

		} mappable_gmadr;	/* aperture */

		/* GMADR register balooning */

		struct {

			uint32_t base;

			uint32_t size;

		} nonmappable_gmadr;	/* non aperture */

		/* allowed fence registers */

		uint32_t fence_num;

		uint32_t rsv2[3];

	} avail_rs;		/* available/assigned resource */

	uint32_t rsv3[0x200 - 24];	/* pad to half page */

	/*

	 * The bottom half page is for response from Gfx driver to hypervisor.

	 * Set to reserved fields temporarily by now.

	 */

	uint32_t rsv4;

	uint32_t display_ready;	/* ready for display owner switch */

	uint32_t rsv5[0x200 - 2];	/* pad to one page */

} __packed;



#define vgtif_reg(x) \

	(VGT_PVINFO_PAGE + (long)&((struct vgt_if *)NULL)->x)



extern void i915_check_vgpu(struct drm_device *dev);



#endif /* _I915_VGPU_H_ */

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