Commit cf8182fc authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge tag 'ti-k3-dt-for-v5.9' of... 

Merge tag 'ti-k3-dt-for-v5.9' of git://git.kernel.org/pub/scm/linux/kernel/git/kristo/linux into arm/dt

Texas Instruments K3 SoC DT updates for v5.9

- Add platforms chipid nodes for am65x and j721e
- Update latest data sheet values for MMC on am65x
- Add serdes and usb3 support for j721e
- Add analog audio support for j721e
- Add SD card support for am65x
- Rename DT nodes for gic-its/smmu to their standard counterparts am65x/j721e
- HTTP links replaced with HTTPS ones

* tag 'ti-k3-dt-for-v5.9' of git://git.kernel.org/pub/scm/linux/kernel/git/kristo/linux:
  arm64: dts: k3-j721e-proc-board: Add wait time for sampling Type-C DIR line
  arm64: dts: ti: k3-j721e: Enable Super-Speed support for USB0
  arm64: dts: ti: k3-j721e-main.dtsi: Add USB to SERDES MUX
  arm64: dts: ti: k3-j721e-main: Add system controller node and SERDES lane mux
  arm64: dts: ti: k3-j721e-main: Add WIZ and SERDES PHY nodes
  dt-bindings: mfd: ti,j721e-system-controller.yaml: Add J721e system controller
  arm64: dts: ti: k3-am65/j721e-main: rename gic-its node to msi-controller
  arm64: dts: ti: k3-j721e-main: rename smmu node to iommu
  arm64: dts: ti: k3-*: Replace HTTP links with HTTPS ones
  arm64: dts: ti: k3-am654-base-board: Add support for SD card
  arm64: dts: ti: k3-am65-main: Add support for sdhci1
  arm64: dts: ti: j721e-common-proc-board: Analog audio support
  arm64: dts: ti: k3-j721e-common-proc-board: Remove duplicated main_i2c1_exp4_pins_default
  arm64: dts: ti: k3-am654-main: Update otap-del-sel values
  arm64: dts: ti: k3-j721e-mcu-wakeup: add k3 platforms chipid module node
  arm64: dts: ti: k3-am65-wakeup: add k3 platforms chipid module node

Link: https://lore.kernel.org/r/3b3b9214-769d-ba1b-db5e-44414a8c5756@ti.com


Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents 0183b9b0 04fe6477

Documentation/devicetree/bindings/mfd/ti,j721e-system-controller.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

# Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/

%YAML 1.2

---

$id: http://devicetree.org/schemas/mfd/ti,j721e-system-controller.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: TI J721e System Controller Registers R/W Device Tree Bindings



description: |

  This represents the Control Module registers (CTRL_MMR0) on the SoC.

  System controller node represents a register region containing a set

  of miscellaneous registers. The registers are not cohesive enough to

  represent as any specific type of device. The typical use-case is

  for some other node's driver, or platform-specific code, to acquire

  a reference to the syscon node (e.g. by phandle, node path, or

  search using a specific compatible value), interrogate the node (or

  associated OS driver) to determine the location of the registers,

  and access the registers directly.



maintainers:

  - Kishon Vijay Abraham I <kishon@ti.com>

  - Roger Quadros <rogerq@ti.com



properties:

  compatible:

    anyOf:

      - items:

        - enum:

           - ti,j721e-system-controller

        - const: syscon

        - const: simple-mfd



  "#address-cells":

    const: 1



  "#size-cells":

    const: 1



  ranges: true



# Optional children



  "^serdes-ln-ctrl@[0-9a-f]+$":

    type: object

    description: |

      This is the SERDES lane control mux. It should follow the bindings

      specified in

      Documentation/devicetree/bindings/mux/reg-mux.txt



required:

  - compatible

  - reg

  - "#address-cells"

  - "#size-cells"

  - ranges



unevaluatedProperties: false



examples:

  - |

    scm_conf: scm-conf@100000 {

        compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";

        reg = <0x00100000 0x1c000>;

        #address-cells = <1>;

        #size-cells = <1>;

        ranges;



        serdes_ln_ctrl: serdes-ln-ctrl@4080 {

            compatible = "mmio-mux";

            reg = <0x00004080 0x50>;

        };

    };

...

arch/arm64/boot/dts/ti/Makefile

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@@ -3,7 +3,7 @@ 
# Make file to build device tree binaries for boards based on

# Texas Instruments Inc processors

#

# Copyright (C) 2016-2018 Texas Instruments Incorporated - http://www.ti.com/

# Copyright (C) 2016-2018 Texas Instruments Incorporated - https://www.ti.com/

#



dtb-$(CONFIG_ARCH_K3_AM6_SOC) += k3-am654-base-board.dtb

arch/arm64/boot/dts/ti/k3-am65-main.dtsi

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@@ -2,7 +2,7 @@ 
/*

 * Device Tree Source for AM6 SoC Family Main Domain peripherals

 *

 * Copyright (C) 2016-2018 Texas Instruments Incorporated - http://www.ti.com/

 * Copyright (C) 2016-2018 Texas Instruments Incorporated - https://www.ti.com/

 */

#include <dt-bindings/phy/phy-am654-serdes.h>
@@ -42,7 +42,7 @@ 
		 */

		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;



		gic_its: gic-its@1820000 {

		gic_its: msi-controller@1820000 {

			compatible = "arm,gic-v3-its";

			reg = <0x00 0x01820000 0x00 0x10000>;

			socionext,synquacer-pre-its = <0x1000000 0x400000>;
@@ -244,9 +244,43 @@ 
		interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;

		mmc-ddr-1_8v;

		mmc-hs200-1_8v;

		ti,otap-del-sel-legacy = <0x0>;

		ti,otap-del-sel-mmc-hs = <0x0>;

		ti,otap-del-sel-sd-hs = <0x0>;

		ti,otap-del-sel-sdr12 = <0x0>;

		ti,otap-del-sel-sdr25 = <0x0>;

		ti,otap-del-sel-sdr50 = <0x8>;

		ti,otap-del-sel-sdr104 = <0x7>;

		ti,otap-del-sel-ddr50 = <0x5>;

		ti,otap-del-sel-ddr52 = <0x5>;

		ti,otap-del-sel-hs200 = <0x5>;

		ti,otap-del-sel-hs400 = <0x0>;

		ti,trm-icp = <0x8>;

		dma-coherent;

	};



	sdhci1: sdhci@4fa0000 {

		compatible = "ti,am654-sdhci-5.1";

		reg = <0x0 0x4fa0000 0x0 0x260>, <0x0 0x4fb0000 0x0 0x134>;

		power-domains = <&k3_pds 48 TI_SCI_PD_EXCLUSIVE>;

		clocks = <&k3_clks 48 0>, <&k3_clks 48 1>;

		clock-names = "clk_ahb", "clk_xin";

		interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;

		ti,otap-del-sel-legacy = <0x0>;

		ti,otap-del-sel-mmc-hs = <0x0>;

		ti,otap-del-sel-sd-hs = <0x0>;

		ti,otap-del-sel-sdr12 = <0x0>;

		ti,otap-del-sel-sdr25 = <0x0>;

		ti,otap-del-sel-sdr50 = <0x8>;

		ti,otap-del-sel-sdr104 = <0x7>;

		ti,otap-del-sel-ddr50 = <0x4>;

		ti,otap-del-sel-ddr52 = <0x4>;

		ti,otap-del-sel-hs200 = <0x7>;

		ti,clkbuf-sel = <0x7>;

		ti,otap-del-sel = <0x2>;

		ti,trm-icp = <0x8>;

		dma-coherent;

		no-1-8-v;

	};



	scm_conf: scm_conf@100000 {

arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi

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@@ -2,7 +2,7 @@ 
/*

 * Device Tree Source for AM6 SoC Family MCU Domain peripherals

 *

 * Copyright (C) 2016-2018 Texas Instruments Incorporated - http://www.ti.com/

 * Copyright (C) 2016-2018 Texas Instruments Incorporated - https://www.ti.com/

 */



&cbass_mcu {

arch/arm64/boot/dts/ti/k3-am65-wakeup.dtsi

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@@ -2,7 +2,7 @@ 
/*

 * Device Tree Source for AM6 SoC Family Wakeup Domain peripherals

 *

 * Copyright (C) 2016-2018 Texas Instruments Incorporated - http://www.ti.com/

 * Copyright (C) 2016-2018 Texas Instruments Incorporated - https://www.ti.com/

 */



&cbass_wakeup {
@@ -34,6 +34,11 @@ 
		};

	};



	chipid@43000014 {

		compatible = "ti,am654-chipid";

		reg = <0x43000014 0x4>;

	};



	wkup_pmx0: pinmux@4301c000 {

		compatible = "pinctrl-single";

		reg = <0x4301c000 0x118>;

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