Commit cf58b746 authored by Cédric Le Goater's avatar Cédric Le Goater Committed by Michael Ellerman
Browse files

powerpc/xive: Remove P9 DD1 flag XIVE_IRQ_FLAG_EOI_FW 

This flag was used to support the P9 DD1 and we have stopped
supporting this CPU when DD2 came out. See skiboot commit:

  https://github.com/open-power/skiboot/commit/0b0d15e3c170



Also, remove eoi handler which is now unused.

Signed-off-by: default avatarCédric Le Goater <clg@kaod.org>
Reviewed-by: default avatarGreg Kurz <groug@kaod.org>
Signed-off-by: default avatarMichael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20201210171450.1933725-11-clg@kaod.org
parent b5277d18

arch/powerpc/include/asm/opal-api.h

+1 −1
Original line number Diff line number Diff line
@@ -1093,7 +1093,7 @@ enum { 
	OPAL_XIVE_IRQ_LSI		= 0x00000004,

	OPAL_XIVE_IRQ_SHIFT_BUG		= 0x00000008, /* P9 DD1.0 workaround */

	OPAL_XIVE_IRQ_MASK_VIA_FW	= 0x00000010, /* P9 DD1.0 workaround */

	OPAL_XIVE_IRQ_EOI_VIA_FW	= 0x00000020,

	OPAL_XIVE_IRQ_EOI_VIA_FW	= 0x00000020, /* P9 DD1.0 workaround */

};



/* Flags for OPAL_XIVE_GET/SET_QUEUE_INFO */

arch/powerpc/include/asm/xive.h

+1 −1
Original line number Diff line number Diff line
@@ -62,7 +62,7 @@ struct xive_irq_data { 
#define XIVE_IRQ_FLAG_LSI	0x02

/* #define XIVE_IRQ_FLAG_SHIFT_BUG	0x04 */ /* P9 DD1.0 workaround */

/* #define XIVE_IRQ_FLAG_MASK_FW	0x08 */ /* P9 DD1.0 workaround */

#define XIVE_IRQ_FLAG_EOI_FW	0x10

/* #define XIVE_IRQ_FLAG_EOI_FW	0x10 */ /* P9 DD1.0 workaround */

#define XIVE_IRQ_FLAG_H_INT_ESB	0x20



/* Special flag set by KVM for excalation interrupts */

arch/powerpc/kvm/book3s_xive_template.c

+0 −2
Original line number Diff line number Diff line
@@ -74,8 +74,6 @@ static void GLUE(X_PFX,source_eoi)(u32 hw_irq, struct xive_irq_data *xd) 
	/* If the XIVE supports the new "store EOI facility, use it */

	if (xd->flags & XIVE_IRQ_FLAG_STORE_EOI)

		__x_writeq(0, __x_eoi_page(xd) + XIVE_ESB_STORE_EOI);

	else if (hw_irq && xd->flags & XIVE_IRQ_FLAG_EOI_FW)

		opal_int_eoi(hw_irq);

	else if (xd->flags & XIVE_IRQ_FLAG_LSI) {

		/*

		 * For LSIs the HW EOI cycle is used rather than PQ bits,

arch/powerpc/sysdev/xive/common.c

+1 −13
Original line number Diff line number Diff line
@@ -354,18 +354,7 @@ static void xive_do_source_eoi(u32 hw_irq, struct xive_irq_data *xd) 
	/* If the XIVE supports the new "store EOI facility, use it */

	if (xd->flags & XIVE_IRQ_FLAG_STORE_EOI)

		xive_esb_write(xd, XIVE_ESB_STORE_EOI, 0);

	else if (hw_irq && xd->flags & XIVE_IRQ_FLAG_EOI_FW) {

		/*

		 * The FW told us to call it. This happens for some

		 * interrupt sources that need additional HW whacking

		 * beyond the ESB manipulation. For example LPC interrupts

		 * on P9 DD1.0 needed a latch to be clared in the LPC bridge

		 * itself. The Firmware will take care of it.

		 */

		if (WARN_ON_ONCE(!xive_ops->eoi))

			return;

		xive_ops->eoi(hw_irq);

	} else {

	else {

		u8 eoi_val;



		/*
@@ -1267,7 +1256,6 @@ static const struct { 
} xive_irq_flags[] = {

	{ XIVE_IRQ_FLAG_STORE_EOI, "STORE_EOI" },

	{ XIVE_IRQ_FLAG_LSI,       "LSI"       },

	{ XIVE_IRQ_FLAG_EOI_FW,    "EOI_FW"    },

	{ XIVE_IRQ_FLAG_H_INT_ESB, "H_INT_ESB" },

	{ XIVE_IRQ_FLAG_NO_EOI,    "NO_EOI"    },

};

arch/powerpc/sysdev/xive/native.c

+0 −12
Original line number Diff line number Diff line
@@ -64,8 +64,6 @@ int xive_native_populate_irq_data(u32 hw_irq, struct xive_irq_data *data) 
		data->flags |= XIVE_IRQ_FLAG_STORE_EOI;

	if (opal_flags & OPAL_XIVE_IRQ_LSI)

		data->flags |= XIVE_IRQ_FLAG_LSI;

	if (opal_flags & OPAL_XIVE_IRQ_EOI_VIA_FW)

		data->flags |= XIVE_IRQ_FLAG_EOI_FW;

	data->eoi_page = be64_to_cpu(eoi_page);

	data->trig_page = be64_to_cpu(trig_page);

	data->esb_shift = be32_to_cpu(esb_shift);
@@ -380,15 +378,6 @@ static void xive_native_update_pending(struct xive_cpu *xc) 
	}

}



static void xive_native_eoi(u32 hw_irq)

{

	/*

	 * Not normally used except if specific interrupts need

	 * a workaround on EOI.

	 */

	opal_int_eoi(hw_irq);

}



static void xive_native_setup_cpu(unsigned int cpu, struct xive_cpu *xc)

{

	s64 rc;
@@ -471,7 +460,6 @@ static const struct xive_ops xive_native_ops = { 
	.match			= xive_native_match,

	.shutdown		= xive_native_shutdown,

	.update_pending		= xive_native_update_pending,

	.eoi			= xive_native_eoi,

	.setup_cpu		= xive_native_setup_cpu,

	.teardown_cpu		= xive_native_teardown_cpu,

	.sync_source		= xive_native_sync_source,

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