ARM: 8942/1: Revert "8857/1: efi: enable CP15 DMB instructions before cleaning the cache" (cf17a1e3) · Commits · 戴 / test

This reverts commit , which is no longer necessary now that the v7 specific routines take care not to issue CP15 barrier instructions before they are enabled in SCTLR. Signed-off-by:

Ard Biesheuvel <ardb@kernel.org> Signed-off-by:

Russell King <rmk+kernel@armlinux.org.uk>

arch/arm/boot/compressed/head.S

+1 −15

Original line number	Diff line number	Diff line
		@@ -1460,21 +1460,7 @@ ENTRY(efi_stub_entry)

		@ Preserve return value of efi_entry() in r4
		mov r4, r0

		@ our cache maintenance code relies on CP15 barrier instructions
		@ but since we arrived here with the MMU and caches configured
		@ by UEFI, we must check that the CP15BEN bit is set in SCTLR.
		@ Note that this bit is RAO/WI on v6 and earlier, so the ISB in
		@ the enable path will be executed on v7+ only.
		mrc p15, 0, r1, c1, c0, 0 @ read SCTLR
		tst r1, #(1 << 5) @ CP15BEN bit set?
		bne 0f
		orr r1, r1, #(1 << 5) @ CP15 barrier instructions
		mcr p15, 0, r1, c1, c0, 0 @ write SCTLR
		ARM( .inst 0xf57ff06f @ v7+ isb )
		THUMB( isb )

		0: bl cache_clean_flush
		bl cache_clean_flush
		bl cache_off

		@ Set parameters for booting zImage according to boot protocol

Admin message