Merge tag 'pinctrl-v5.1-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl

Required properties for iomux controller:

- compatible: "atmel,at91rm9200-pinctrl" or "atmel,at91sam9x5-pinctrl"

		or "atmel,sama5d3-pinctrl"

		or "atmel,sama5d3-pinctrl" or "microchip,sam9x60-pinctrl"

- atmel,mux-mask: array of mask (periph per bank) to describe if a pin can be

  configured in this periph mode. All the periph and bank need to be describe.

				11 - High

OUTPUT		(1 << 7): indicate this pin need to be configured as an output.

OUTPUT_VAL	(1 << 8): output val (1 = high, 0 = low)

SLEWRATE	(1 << 9): slew rate of the pin: 0 = disable, 1 = enable

DEBOUNCE	(1 << 16): indicate this pin needs debounce.

DEBOUNCE_VAL	(0x3fff << 17): debounce value.

   configurations by referring to the phandle of that pin configuration node.

4. The gpio controller must be describe in the pinctrl simple-bus.

For each bank the required properties are:

- compatible: "atmel,at91sam9x5-gpio" or "atmel,at91rm9200-gpio" or

  "microchip,sam9x60-gpio"

- reg: physical base address and length of the controller's registers

- interrupts: interrupt outputs from the controller

- interrupt-controller: marks the device node as an interrupt controller

- #interrupt-cells: should be 2; refer to ../interrupt-controller/interrupts.txt

  for more details.

- gpio-controller

- #gpio-cells: should be 2; the first cell is the GPIO number and the second

  cell specifies GPIO flags as defined in <dt-bindings/gpio/gpio.h>.

- clocks: bank clock

Examples:

pinctrl@fffff400 {

	compatible = "atmel,at91rm9200-pinctrl", "simple-bus";

	reg = <0xfffff400 0x600>;

	pioA: gpio@fffff400 {

		compatible = "atmel,at91sam9x5-gpio";

		reg = <0xfffff400 0x200>;

		interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;

		#gpio-cells = <2>;

		gpio-controller;

		interrupt-controller;

		#interrupt-cells = <2>;

		clocks = <&pmc PMC_TYPE_PERIPHERAL 2>;

	};

	atmel,mux-mask = <

	      /*    A         B     */

	       0xffffffff 0xffc00c3b  /* pioA */

* Freescale IMX50 IOMUX Controller

Please refer to fsl,imx-pinctrl.txt in this directory for common binding part

and usage.

Required properties:

- compatible: "fsl,imx50-iomuxc"

- fsl,pins: two integers array, represents a group of pins mux and config

  setting. The format is fsl,pins = <PIN_FUNC_ID CONFIG>, PIN_FUNC_ID is a

  pin working on a specific function, CONFIG is the pad setting value like

  pull-up for this pin. Please refer to imx50 datasheet for the valid pad

  config settings.

CONFIG bits definition:

PAD_CTL_HVE			(1 << 13)

PAD_CTL_HYS			(1 << 8)

PAD_CTL_PKE			(1 << 7)

PAD_CTL_PUE			(1 << 6)

PAD_CTL_PUS_100K_DOWN		(0 << 4)

PAD_CTL_PUS_47K_UP		(1 << 4)

PAD_CTL_PUS_100K_UP		(2 << 4)

PAD_CTL_PUS_22K_UP		(3 << 4)

PAD_CTL_ODE			(1 << 3)

PAD_CTL_DSE_LOW			(0 << 1)

PAD_CTL_DSE_MED			(1 << 1)

PAD_CTL_DSE_HIGH		(2 << 1)

PAD_CTL_DSE_MAX			(3 << 1)

PAD_CTL_SRE_FAST		(1 << 0)

PAD_CTL_SRE_SLOW		(0 << 0)

Refer to imx50-pinfunc.h in device tree source folder for all available

imx50 PIN_FUNC_ID.

* Freescale IMX8MM IOMUX Controller

Please refer to fsl,imx-pinctrl.txt and pinctrl-bindings.txt in this directory

for common binding part and usage.

Required properties:

- compatible: "fsl,imx8mm-iomuxc"

- reg: should contain the base physical address and size of the iomuxc

  registers.

Required properties in sub-nodes:

- fsl,pins: each entry consists of 6 integers and represents the mux and config

  setting for one pin.  The first 5 integers <mux_reg conf_reg input_reg mux_val

  input_val> are specified using a PIN_FUNC_ID macro, which can be found in

  <dt-bindings/pinctrl/imx8mm-pinfunc.h>. The last integer CONFIG is

  the pad setting value like pull-up on this pin.  Please refer to i.MX8M Mini

  Reference Manual for detailed CONFIG settings.

Examples:

&uart1 {

       pinctrl-names = "default";

       pinctrl-0 = <&pinctrl_uart1>;

};

iomuxc: pinctrl@30330000 {

        compatible = "fsl,imx8mm-iomuxc";

        reg = <0x0 0x30330000 0x0 0x10000>;

        pinctrl_uart1: uart1grp {

                fsl,pins = <

                        MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX             0x140

                        MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX             0x140

                >;

        };

};

 - functions pwm, gpio

group pmic1

 - pin 17

 - pin 7

 - functions pmic, gpio

group pmic0

 - pin 16

 - pin 6

 - functions pmic, gpio

group i2c2

 - functions drvbus, gpio

group sdio_sb

 - pins 60-64

 - pins 60-65

 - functions sdio, gpio

group rgmii

 - pins 42-55

 - pins 42-53

 - functions mii, gpio

group pcie1

 - pins 39-40

 - pins 39

 - functions pcie, gpio

group pcie1_clkreq

 - pins 40

 - functions pcie, gpio

group pcie1_wakeup

 - pins 41

 - functions pcie, gpio

group smi

 - pins 54-55

 - functions smi, gpio

group ptp

 - pins 56-58

 - pins 56

 - functions ptp, gpio

group ptp_clk

GPIO controller.

Required properties for sub-nodes are:

 - reg: should contain address and size for mux, pull-enable, pull and

   gpio register sets

 - reg-names: an array of strings describing the "reg" entries. Must

   contain "mux", "pull" and "gpio". "pull-enable" is optional and

   when it is missing the "pull" registers are used instead

 - reg: should contain a list of address and size, one tuple for each entry

   in reg-names.

 - reg-names: an array of strings describing the "reg" entries.

   Must contain "mux" and "gpio".

   May contain "pull", "pull-enable" and "ds" when appropriate.

 - gpio-controller: identifies the node as a gpio controller

 - #gpio-cells: must be 2