Commit cecddda7 authored by Andy Shevchenko's avatar Andy Shevchenko
Browse files

pinctrl: lynxpoint: Add pin control data structures 



In order to implement pin control for Intel Lynxpoint, we need
data structures in which to store and pass along pin, community
and SoC data information.

Reviewed-by: default avatarLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: default avatarAndy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: default avatarMika Westerberg <mika.westerberg@linux.intel.com>
parent 54d371cf

drivers/pinctrl/intel/pinctrl-lynxpoint.c

+124 −2
Original line number Diff line number Diff line
@@ -18,6 +18,128 @@ 
#include <linux/slab.h>

#include <linux/types.h>



#include <linux/pinctrl/pinctrl.h>

#include <linux/pinctrl/pinmux.h>

#include <linux/pinctrl/pinconf.h>

#include <linux/pinctrl/pinconf-generic.h>



#include "pinctrl-intel.h"



#define COMMUNITY(p, n)			\

	{				\

		.pin_base	= (p),	\

		.npins		= (n),	\

	}



static const struct pinctrl_pin_desc lptlp_pins[] = {

	PINCTRL_PIN(0, "GP0_UART1_RXD"),

	PINCTRL_PIN(1, "GP1_UART1_TXD"),

	PINCTRL_PIN(2, "GP2_UART1_RTSB"),

	PINCTRL_PIN(3, "GP3_UART1_CTSB"),

	PINCTRL_PIN(4, "GP4_I2C0_SDA"),

	PINCTRL_PIN(5, "GP5_I2C0_SCL"),

	PINCTRL_PIN(6, "GP6_I2C1_SDA"),

	PINCTRL_PIN(7, "GP7_I2C1_SCL"),

	PINCTRL_PIN(8, "GP8"),

	PINCTRL_PIN(9, "GP9"),

	PINCTRL_PIN(10, "GP10"),

	PINCTRL_PIN(11, "GP11_SMBALERTB"),

	PINCTRL_PIN(12, "GP12_LANPHYPC"),

	PINCTRL_PIN(13, "GP13"),

	PINCTRL_PIN(14, "GP14"),

	PINCTRL_PIN(15, "GP15"),

	PINCTRL_PIN(16, "GP16_MGPIO9"),

	PINCTRL_PIN(17, "GP17_MGPIO10"),

	PINCTRL_PIN(18, "GP18_SRC0CLKRQB"),

	PINCTRL_PIN(19, "GP19_SRC1CLKRQB"),

	PINCTRL_PIN(20, "GP20_SRC2CLKRQB"),

	PINCTRL_PIN(21, "GP21_SRC3CLKRQB"),

	PINCTRL_PIN(22, "GP22_SRC4CLKRQB_TRST2"),

	PINCTRL_PIN(23, "GP23_SRC5CLKRQB_TDI2"),

	PINCTRL_PIN(24, "GP24_MGPIO0"),

	PINCTRL_PIN(25, "GP25_USBWAKEOUTB"),

	PINCTRL_PIN(26, "GP26_MGPIO5"),

	PINCTRL_PIN(27, "GP27_MGPIO6"),

	PINCTRL_PIN(28, "GP28_MGPIO7"),

	PINCTRL_PIN(29, "GP29_SLP_WLANB_MGPIO3"),

	PINCTRL_PIN(30, "GP30_SUSWARNB_SUSPWRDNACK_MGPIO1"),

	PINCTRL_PIN(31, "GP31_ACPRESENT_MGPIO2"),

	PINCTRL_PIN(32, "GP32_CLKRUNB"),

	PINCTRL_PIN(33, "GP33_DEVSLP0"),

	PINCTRL_PIN(34, "GP34_SATA0XPCIE6L3B_SATA0GP"),

	PINCTRL_PIN(35, "GP35_SATA1XPCIE6L2B_SATA1GP"),

	PINCTRL_PIN(36, "GP36_SATA2XPCIE6L1B_SATA2GP"),

	PINCTRL_PIN(37, "GP37_SATA3XPCIE6L0B_SATA3GP"),

	PINCTRL_PIN(38, "GP38_DEVSLP1"),

	PINCTRL_PIN(39, "GP39_DEVSLP2"),

	PINCTRL_PIN(40, "GP40_OC0B"),

	PINCTRL_PIN(41, "GP41_OC1B"),

	PINCTRL_PIN(42, "GP42_OC2B"),

	PINCTRL_PIN(43, "GP43_OC3B"),

	PINCTRL_PIN(44, "GP44"),

	PINCTRL_PIN(45, "GP45_TMS2"),

	PINCTRL_PIN(46, "GP46_TDO2"),

	PINCTRL_PIN(47, "GP47"),

	PINCTRL_PIN(48, "GP48"),

	PINCTRL_PIN(49, "GP49"),

	PINCTRL_PIN(50, "GP50"),

	PINCTRL_PIN(51, "GP51_GSXDOUT"),

	PINCTRL_PIN(52, "GP52_GSXSLOAD"),

	PINCTRL_PIN(53, "GP53_GSXDIN"),

	PINCTRL_PIN(54, "GP54_GSXSRESETB"),

	PINCTRL_PIN(55, "GP55_GSXCLK"),

	PINCTRL_PIN(56, "GP56"),

	PINCTRL_PIN(57, "GP57"),

	PINCTRL_PIN(58, "GP58"),

	PINCTRL_PIN(59, "GP59"),

	PINCTRL_PIN(60, "GP60_SML0ALERTB_MGPIO4"),

	PINCTRL_PIN(61, "GP61_SUS_STATB"),

	PINCTRL_PIN(62, "GP62_SUSCLK"),

	PINCTRL_PIN(63, "GP63_SLP_S5B"),

	PINCTRL_PIN(64, "GP64_SDIO_CLK"),

	PINCTRL_PIN(65, "GP65_SDIO_CMD"),

	PINCTRL_PIN(66, "GP66_SDIO_D0"),

	PINCTRL_PIN(67, "GP67_SDIO_D1"),

	PINCTRL_PIN(68, "GP68_SDIO_D2"),

	PINCTRL_PIN(69, "GP69_SDIO_D3"),

	PINCTRL_PIN(70, "GP70_SDIO_POWER_EN"),

	PINCTRL_PIN(71, "GP71_MPHYPC"),

	PINCTRL_PIN(72, "GP72_BATLOWB"),

	PINCTRL_PIN(73, "GP73_SML1ALERTB_PCHHOTB_MGPIO8"),

	PINCTRL_PIN(74, "GP74_SML1DATA_MGPIO12"),

	PINCTRL_PIN(75, "GP75_SML1CLK_MGPIO11"),

	PINCTRL_PIN(76, "GP76_BMBUSYB"),

	PINCTRL_PIN(77, "GP77_PIRQAB"),

	PINCTRL_PIN(78, "GP78_PIRQBB"),

	PINCTRL_PIN(79, "GP79_PIRQCB"),

	PINCTRL_PIN(80, "GP80_PIRQDB"),

	PINCTRL_PIN(81, "GP81_SPKR"),

	PINCTRL_PIN(82, "GP82_RCINB"),

	PINCTRL_PIN(83, "GP83_GSPI0_CSB"),

	PINCTRL_PIN(84, "GP84_GSPI0_CLK"),

	PINCTRL_PIN(85, "GP85_GSPI0_MISO"),

	PINCTRL_PIN(86, "GP86_GSPI0_MOSI"),

	PINCTRL_PIN(87, "GP87_GSPI1_CSB"),

	PINCTRL_PIN(88, "GP88_GSPI1_CLK"),

	PINCTRL_PIN(89, "GP89_GSPI1_MISO"),

	PINCTRL_PIN(90, "GP90_GSPI1_MOSI"),

	PINCTRL_PIN(91, "GP91_UART0_RXD"),

	PINCTRL_PIN(92, "GP92_UART0_TXD"),

	PINCTRL_PIN(93, "GP93_UART0_RTSB"),

	PINCTRL_PIN(94, "GP94_UART0_CTSB"),

};



static const struct intel_community lptlp_communities[] = {

	COMMUNITY(0, 95),

};



static const struct intel_pinctrl_soc_data lptlp_soc_data = {

	.pins		= lptlp_pins,

	.npins		= ARRAY_SIZE(lptlp_pins),

	.communities	= lptlp_communities,

	.ncommunities	= ARRAY_SIZE(lptlp_communities),

};



/* LynxPoint chipset has support for 95 GPIO pins */



#define LP_NUM_GPIO	95
@@ -477,8 +599,8 @@ static const struct dev_pm_ops lp_gpio_pm_ops = { 
};



static const struct acpi_device_id lynxpoint_gpio_acpi_match[] = {

	{ "INT33C7", 0 },

	{ "INT3437", 0 },

	{ "INT33C7", (kernel_ulong_t)&lptlp_soc_data },

	{ "INT3437", (kernel_ulong_t)&lptlp_soc_data },

	{ }

};

MODULE_DEVICE_TABLE(acpi, lynxpoint_gpio_acpi_match);

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