Commit cecb9a1e authored by Olof Johansson's avatar Olof Johansson
Browse files

Merge tag 'imx-dt-3.7' of git://git.linaro.org/people/shawnguo/linux-2.6 into next/dt 

- All imx53 board files are removed by the equal device tree support
- The efikamx board files are removed to ease device tree migration
- Remove dummy pinctrl state by setting up pinctrl in device tree

* tag 'imx-dt-3.7' of git://git.linaro.org/people/shawnguo/linux-2.6: (28 commits)
  ARM: imx6q-sabrelite: Rename 'pinctrl_gpio_hog'
  ARM: imx51: decouple device tree boot from board files
  ARM: imx51: build in pinctrl support
  ARM: dts: imx51-babbage: add pinctrl settings
  ARM: imx53: remove unneeded files and functions
  ARM: imx53: support device tree boot only
  ARM: imx53: decouple device tree boot from board files
  ARM: imx53: build in pinctrl support
  ARM: dts: imx53-smd: add pinctrl settings
  ARM: dts: imx53-evk: add pinctrl settings
  ARM: dts: imx53-ard: add pinctrl settings
  ARM: dts: imx53-qsb: add pinctrl settings
  ARM: imx6q: remove dummy pinctrl state
  ARM: dts: imx6q-sabresd: add pinctrl settings
  ARM: dts: imx6q-arm2: add pinctrl for uart and enet
  ARM: dts: imx6q-sabrelite: add pinctrl for usdhc and enet
  ARM: dts: imx6q: sort iomuxc sub-nodes in name
  ARM: dts: imx6q: name iomuxc sub-nodes following pin function
  ARM: dts: imx6q: improve indentation for fsl,pins
  ARM: efikamx: remove Genesi Efika MX platform files from the tree
  ...

Resolved trivial context conflict in arch/arm/boot/dts/imx51-babbage.dts
parents 83ae0ffa f8135a74

arch/arm/boot/dts/imx27-phytec-phycore.dts

+0 −4
Original line number Diff line number Diff line
@@ -23,10 +23,6 @@ 
	soc {

		aipi@10000000 { /* aipi */



			wdog@10002000 {

				status = "okay";

			};



			serial@1000a000 {

				fsl,uart-has-rtscts;

				status = "okay";

arch/arm/boot/dts/imx27.dtsi

+0 −1
Original line number Diff line number Diff line
@@ -62,7 +62,6 @@ 
				compatible = "fsl,imx27-wdt", "fsl,imx21-wdt";

				reg = <0x10002000 0x4000>;

				interrupts = <27>;

				status = "disabled";

			};



			uart1: serial@1000a000 {

arch/arm/boot/dts/imx51-babbage.dts

+34 −10
Original line number Diff line number Diff line
@@ -25,23 +25,31 @@ 
		aips@70000000 { /* aips-1 */

			spba@70000000 {

				esdhc@70004000 { /* ESDHC1 */

					pinctrl-names = "default";

					pinctrl-0 = <&pinctrl_esdhc1_1>;

					fsl,cd-controller;

					fsl,wp-controller;

					status = "okay";

				};



				esdhc@70008000 { /* ESDHC2 */

					pinctrl-names = "default";

					pinctrl-0 = <&pinctrl_esdhc2_1>;

					cd-gpios = <&gpio1 6 0>;

					wp-gpios = <&gpio1 5 0>;

					status = "okay";

				};



				uart3: serial@7000c000 {

					pinctrl-names = "default";

					pinctrl-0 = <&pinctrl_uart3_1>;

					fsl,uart-has-rtscts;

					status = "okay";

				};



				ecspi@70010000 { /* ECSPI1 */

					pinctrl-names = "default";

					pinctrl-0 = <&pinctrl_ecspi1_1>;

					fsl,spi-num-chipselects = <2>;

					cs-gpios = <&gpio4 24 0>, <&gpio4 25 0>;

					status = "okay";
@@ -169,31 +177,43 @@ 
				};

			};



			wdog@73f98000 { /* WDOG1 */

				status = "okay";

			};



			iomuxc@73fa8000 {

				compatible = "fsl,imx51-iomuxc-babbage";

				reg = <0x73fa8000 0x4000>;

				pinctrl-names = "default";

				pinctrl-0 = <&pinctrl_hog>;



				hog {

					pinctrl_hog: hoggrp {

						fsl,pins = <

							694  0x20d5	/* MX51_PAD_GPIO1_0__SD1_CD */

							697  0x20d5	/* MX51_PAD_GPIO1_1__SD1_WP */

							737  0x100	/* MX51_PAD_GPIO1_5__GPIO1_5 */

							740  0x100	/* MX51_PAD_GPIO1_6__GPIO1_6 */

							121  0x5	/* MX51_PAD_EIM_A27__GPIO2_21 */

							402  0x85	/* MX51_PAD_CSPI1_SS0__GPIO4_24 */

							405  0x85	/* MX51_PAD_CSPI1_SS1__GPIO4_25 */

						>;

					};

				};

			};



			uart1: serial@73fbc000 {

				pinctrl-names = "default";

				pinctrl-0 = <&pinctrl_uart1_1>;

				fsl,uart-has-rtscts;

				status = "okay";

			};



			uart2: serial@73fc0000 {

				pinctrl-names = "default";

				pinctrl-0 = <&pinctrl_uart2_1>;

				status = "okay";

			};

		};



		aips@80000000 {	/* aips-2 */

			sdma@83fb0000 {

				fsl,sdma-ram-script-name = "imx/sdma/sdma-imx51.bin";

			};



			i2c@83fc4000 { /* I2C2 */

				pinctrl-names = "default";

				pinctrl-0 = <&pinctrl_i2c2_1>;

				status = "okay";



				sgtl5000: codec@0a {
@@ -206,10 +226,14 @@ 
			};



			audmux@83fd0000 {

				pinctrl-names = "default";

				pinctrl-0 = <&pinctrl_audmux_1>;

				status = "okay";

			};



			ethernet@83fec000 {

				pinctrl-names = "default";

				pinctrl-0 = <&pinctrl_fec_1>;

				phy-mode = "mii";

				status = "okay";

			};

arch/arm/boot/dts/imx51.dtsi

+145 −1
Original line number Diff line number Diff line
@@ -130,6 +130,34 @@ 
				};

			};



			usb@73f80000 {

				compatible = "fsl,imx51-usb", "fsl,imx27-usb";

				reg = <0x73f80000 0x0200>;

				interrupts = <18>;

				status = "disabled";

			};



			usb@73f80200 {

				compatible = "fsl,imx51-usb", "fsl,imx27-usb";

				reg = <0x73f80200 0x0200>;

				interrupts = <14>;

				status = "disabled";

			};



			usb@73f80400 {

				compatible = "fsl,imx51-usb", "fsl,imx27-usb";

				reg = <0x73f80400 0x0200>;

				interrupts = <16>;

				status = "disabled";

			};



			usb@73f80600 {

				compatible = "fsl,imx51-usb", "fsl,imx27-usb";

				reg = <0x73f80600 0x0200>;

				interrupts = <17>;

				status = "disabled";

			};



			gpio1: gpio@73f84000 {

				compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";

				reg = <0x73f84000 0x4000>;
@@ -174,7 +202,6 @@ 
				compatible = "fsl,imx51-wdt", "fsl,imx21-wdt";

				reg = <0x73f98000 0x4000>;

				interrupts = <58>;

				status = "disabled";

			};



			wdog@73f9c000 { /* WDOG2 */
@@ -184,6 +211,122 @@ 
				status = "disabled";

			};



			iomuxc@73fa8000 {

				compatible = "fsl,imx51-iomuxc";

				reg = <0x73fa8000 0x4000>;



				audmux {

					pinctrl_audmux_1: audmuxgrp-1 {

						fsl,pins = <

							384 0x80000000	/* MX51_PAD_AUD3_BB_TXD__AUD3_TXD */

							386 0x80000000	/* MX51_PAD_AUD3_BB_RXD__AUD3_RXD */

							389 0x80000000	/* MX51_PAD_AUD3_BB_CK__AUD3_TXC */

							391 0x80000000	/* MX51_PAD_AUD3_BB_FS__AUD3_TXFS */

						>;

					};

				};



				fec {

					pinctrl_fec_1: fecgrp-1 {

						fsl,pins = <

							128 0x80000000	/* MX51_PAD_EIM_EB2__FEC_MDIO */

							134 0x80000000	/* MX51_PAD_EIM_EB3__FEC_RDATA1 */

							146 0x80000000	/* MX51_PAD_EIM_CS2__FEC_RDATA2 */

							152 0x80000000	/* MX51_PAD_EIM_CS3__FEC_RDATA3 */

							158 0x80000000	/* MX51_PAD_EIM_CS4__FEC_RX_ER */

							165 0x80000000	/* MX51_PAD_EIM_CS5__FEC_CRS */

							206 0x80000000	/* MX51_PAD_NANDF_RB2__FEC_COL */

							213 0x80000000	/* MX51_PAD_NANDF_RB3__FEC_RX_CLK */

							293 0x80000000	/* MX51_PAD_NANDF_D9__FEC_RDATA0 */

							298 0x80000000	/* MX51_PAD_NANDF_D8__FEC_TDATA0 */

							225 0x80000000	/* MX51_PAD_NANDF_CS2__FEC_TX_ER */

							231 0x80000000	/* MX51_PAD_NANDF_CS3__FEC_MDC */

							237 0x80000000	/* MX51_PAD_NANDF_CS4__FEC_TDATA1 */

							243 0x80000000	/* MX51_PAD_NANDF_CS5__FEC_TDATA2 */

							250 0x80000000	/* MX51_PAD_NANDF_CS6__FEC_TDATA3 */

							255 0x80000000	/* MX51_PAD_NANDF_CS7__FEC_TX_EN */

							260 0x80000000	/* MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK */

						>;

					};

				};



				ecspi1 {

					pinctrl_ecspi1_1: ecspi1grp-1 {

						fsl,pins = <

							398 0x185	/* MX51_PAD_CSPI1_MISO__ECSPI1_MISO */

							394 0x185	/* MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI */

							409 0x185	/* MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK */

						>;

					};

				};



				esdhc1 {

					pinctrl_esdhc1_1: esdhc1grp-1 {

						fsl,pins = <

							666 0x400020d5	/* MX51_PAD_SD1_CMD__SD1_CMD */

							669 0x20d5	/* MX51_PAD_SD1_CLK__SD1_CLK */

							672 0x20d5	/* MX51_PAD_SD1_DATA0__SD1_DATA0 */

							678 0x20d5	/* MX51_PAD_SD1_DATA1__SD1_DATA1 */

							684 0x20d5	/* MX51_PAD_SD1_DATA2__SD1_DATA2 */

							691 0x20d5	/* MX51_PAD_SD1_DATA3__SD1_DATA3 */

						>;

					};

				};



				esdhc2 {

					pinctrl_esdhc2_1: esdhc2grp-1 {

						fsl,pins = <

							704 0x400020d5	/* MX51_PAD_SD2_CMD__SD2_CMD */

							707 0x20d5	/* MX51_PAD_SD2_CLK__SD2_CLK */

							710 0x20d5	/* MX51_PAD_SD2_DATA0__SD2_DATA0 */

							712 0x20d5	/* MX51_PAD_SD2_DATA1__SD2_DATA1 */

							715 0x20d5	/* MX51_PAD_SD2_DATA2__SD2_DATA2 */

							719 0x20d5	/* MX51_PAD_SD2_DATA3__SD2_DATA3 */

						>;

					};

				};



				i2c2 {

					pinctrl_i2c2_1: i2c2grp-1 {

						fsl,pins = <

							449 0x400001ed	/* MX51_PAD_KEY_COL4__I2C2_SCL */

							454 0x400001ed	/* MX51_PAD_KEY_COL5__I2C2_SDA */

						>;

					};

				};



				uart1 {

					pinctrl_uart1_1: uart1grp-1 {

						fsl,pins = <

							413 0x1c5	/* MX51_PAD_UART1_RXD__UART1_RXD */

							416 0x1c5	/* MX51_PAD_UART1_TXD__UART1_TXD */

							418 0x1c5	/* MX51_PAD_UART1_RTS__UART1_RTS */

							420 0x1c5	/* MX51_PAD_UART1_CTS__UART1_CTS */

						>;

					};

				};



				uart2 {

					pinctrl_uart2_1: uart2grp-1 {

						fsl,pins = <

							423 0x1c5	/* MX51_PAD_UART2_RXD__UART2_RXD */

							426 0x1c5	/* MX51_PAD_UART2_TXD__UART2_TXD */

						>;

					};

				};



				uart3 {

					pinctrl_uart3_1: uart3grp-1 {

						fsl,pins = <

							54 0x1c5	/* MX51_PAD_EIM_D25__UART3_RXD */

							59 0x1c5	/* MX51_PAD_EIM_D26__UART3_TXD */

							65 0x1c5	/* MX51_PAD_EIM_D27__UART3_RTS */

							49 0x1c5	/* MX51_PAD_EIM_D24__UART3_CTS */

						>;

					};

				};

			};



			uart1: serial@73fbc000 {

				compatible = "fsl,imx51-uart", "fsl,imx21-uart";

				reg = <0x73fbc000 0x4000>;
@@ -219,6 +362,7 @@ 
				compatible = "fsl,imx51-sdma", "fsl,imx35-sdma";

				reg = <0x83fb0000 0x4000>;

				interrupts = <6>;

				fsl,sdma-ram-script-name = "imx/sdma/sdma-imx51.bin";

			};



			cspi@83fc0000 {

arch/arm/boot/dts/imx53-ard.dts

+47 −12
Original line number Diff line number Diff line
@@ -25,29 +25,64 @@ 
		aips@50000000 { /* AIPS1 */

			spba@50000000 {

				esdhc@50004000 { /* ESDHC1 */

					pinctrl-names = "default";

					pinctrl-0 = <&pinctrl_esdhc1_2>;

					cd-gpios = <&gpio1 1 0>;

					wp-gpios = <&gpio1 9 0>;

					status = "okay";

				};

			};



			wdog@53f98000 { /* WDOG1 */

				status = "okay";

			};



			iomuxc@53fa8000 {

				compatible = "fsl,imx53-iomuxc-ard";

				reg = <0x53fa8000 0x4000>;

				pinctrl-names = "default";

				pinctrl-0 = <&pinctrl_hog>;



				hog {

					pinctrl_hog: hoggrp {

						fsl,pins = <

							1077 0x80000000	/* MX53_PAD_GPIO_1__GPIO1_1 */

							1085 0x80000000	/* MX53_PAD_GPIO_9__GPIO1_9 */

							486  0x80000000	/* MX53_PAD_EIM_EB3__GPIO2_31 */

							739  0x80000000	/* MX53_PAD_GPIO_10__GPIO4_0 */

							218  0x80000000	/* MX53_PAD_DISP0_DAT16__GPIO5_10 */

							226  0x80000000	/* MX53_PAD_DISP0_DAT17__GPIO5_11 */

							233  0x80000000	/* MX53_PAD_DISP0_DAT18__GPIO5_12 */

							241  0x80000000	/* MX53_PAD_DISP0_DAT19__GPIO5_13 */

							429  0x80000000	/* MX53_PAD_EIM_D16__EMI_WEIM_D_16 */

							435  0x80000000	/* MX53_PAD_EIM_D17__EMI_WEIM_D_17 */

							441  0x80000000	/* MX53_PAD_EIM_D18__EMI_WEIM_D_18 */

							448  0x80000000	/* MX53_PAD_EIM_D19__EMI_WEIM_D_19 */

							456  0x80000000	/* MX53_PAD_EIM_D20__EMI_WEIM_D_20 */

							464  0x80000000	/* MX53_PAD_EIM_D21__EMI_WEIM_D_21 */

							471  0x80000000	/* MX53_PAD_EIM_D22__EMI_WEIM_D_22 */

							477  0x80000000	/* MX53_PAD_EIM_D23__EMI_WEIM_D_23 */

							492  0x80000000	/* MX53_PAD_EIM_D24__EMI_WEIM_D_24 */

							500  0x80000000	/* MX53_PAD_EIM_D25__EMI_WEIM_D_25 */

							508  0x80000000	/* MX53_PAD_EIM_D26__EMI_WEIM_D_26 */

							516  0x80000000	/* MX53_PAD_EIM_D27__EMI_WEIM_D_27 */

							524  0x80000000	/* MX53_PAD_EIM_D28__EMI_WEIM_D_28 */

							532  0x80000000	/* MX53_PAD_EIM_D29__EMI_WEIM_D_29 */

							540  0x80000000	/* MX53_PAD_EIM_D30__EMI_WEIM_D_30 */

							548  0x80000000	/* MX53_PAD_EIM_D31__EMI_WEIM_D_31 */

							637  0x80000000	/* MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0 */

							642  0x80000000	/* MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1 */

							647  0x80000000	/* MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2 */

							652  0x80000000	/* MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3 */

							657  0x80000000	/* MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4 */

							662  0x80000000	/* MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5 */

							667  0x80000000	/* MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6 */

							611  0x80000000	/* MX53_PAD_EIM_OE__EMI_WEIM_OE */

							616  0x80000000	/* MX53_PAD_EIM_RW__EMI_WEIM_RW */

							607  0x80000000	/* MX53_PAD_EIM_CS1__EMI_WEIM_CS_1 */

						>;

					};



			uart1: serial@53fbc000 {

				status = "okay";

				};

			};



		aips@60000000 {	/* AIPS2 */

			sdma@63fb0000 {

				fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";

			uart1: serial@53fbc000 {

				pinctrl-names = "default";

				pinctrl-0 = <&pinctrl_uart1_2>;

				status = "okay";

			};

		};

	};

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