Commit ceb3dbb4 authored by Jun Lei's avatar Jun Lei Committed by Alex Deucher
Browse files

drm/amd/display: remove sink reference in dc_stream_state 



[why]
dc_stream_state containing a pointer to sink is poor design.
Sink describes the display, and the specifications or capabilities
it has.  That information is irrelevant for dc_stream_state, which describes
hardware state, and is generally used for hardware programming.  It
could further be argued that dc_sink itself is just a convenience dc
provides, and DC should be perfectly capable of programming hardware
without any dc_sinks (for example, emulated sinks).

[how]
Phase 1:
Deprecate use of dc_sink pointer in dc_stream.  Most references are trivial
to remove, but some call sites are risky (such as is_timing_changed) with
no obvious logical replacement.  These will be removed in follow up change.

Add dc_link pointer to dc_stream.  This is the typical reason DC really needed
sink pointer, and most call sites are replaced with this.

DMs also need minor updates, as all 3 DMs leverage stream->sink for
some functionality.  this is replaced instead by a pointer to private data
inside dc_stream_state, which is used by DMs as a quality of life improvment
for some key functionality.  it allows DMs to set pointers have to their own objects
which associate OS objects to dc_stream_states (such as DisplayTarget
and amdgpu_dm_connector).  Without the private pointer, DMs would be
forced to perform a lookup for callbacks.

Signed-off-by: default avatarJun Lei <Jun.Lei@amd.com>
Reviewed-by: default avatarAric Cyr <Aric.Cyr@amd.com>
Acked-by: default avatarDavid Francis <David.Francis@amd.com>
Acked-by: default avatarLeo Li <sunpeng.li@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 51ba137e

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

+6 −4
Original line number Diff line number Diff line
@@ -2666,10 +2666,10 @@ fill_stream_properties_from_drm_display_mode(struct dc_stream_state *stream, 
	timing_out->v_border_bottom = 0;

	/* TODO: un-hardcode */

	if (drm_mode_is_420_only(info, mode_in)

			&& stream->sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A)

			&& stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)

		timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420;

	else if ((connector->display_info.color_formats & DRM_COLOR_FORMAT_YCRCB444)

			&& stream->sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A)

			&& stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)

		timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR444;

	else

		timing_out->pixel_encoding = PIXEL_ENCODING_RGB;
@@ -2711,7 +2711,7 @@ fill_stream_properties_from_drm_display_mode(struct dc_stream_state *stream, 


	stream->out_transfer_func->type = TF_TYPE_PREDEFINED;

	stream->out_transfer_func->tf = TRANSFER_FUNCTION_SRGB;

	if (stream->sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A)

	if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)

		adjust_colour_depth_from_display_info(timing_out, info);

}
@@ -2905,6 +2905,8 @@ create_stream_for_sink(struct amdgpu_dm_connector *aconnector, 
		goto finish;

	}



	stream->dm_stream_context = aconnector;



	list_for_each_entry(preferred_mode, &aconnector->base.modes, head) {

		/* Search for preferred mode */

		if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED) {
@@ -2956,7 +2958,7 @@ create_stream_for_sink(struct amdgpu_dm_connector *aconnector, 
		drm_connector,

		sink);



	update_stream_signal(stream);

	update_stream_signal(stream, sink);



	if (dm_state && dm_state->freesync_capable)

		stream->ignore_msa_timing_param = true;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

+3 −3
Original line number Diff line number Diff line
@@ -192,7 +192,7 @@ bool dm_helpers_dp_mst_write_payload_allocation_table( 
	int bpp = 0;

	int pbn = 0;



	aconnector = stream->sink->priv;

	aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context;



	if (!aconnector || !aconnector->mst_port)

		return false;
@@ -284,7 +284,7 @@ bool dm_helpers_dp_mst_poll_for_allocation_change_trigger( 
	struct drm_dp_mst_topology_mgr *mst_mgr;

	int ret;



	aconnector = stream->sink->priv;

	aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context;



	if (!aconnector || !aconnector->mst_port)

		return false;
@@ -312,7 +312,7 @@ bool dm_helpers_dp_mst_send_payload_allocation( 
	struct drm_dp_mst_port *mst_port;

	int ret;



	aconnector = stream->sink->priv;

	aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context;



	if (!aconnector || !aconnector->mst_port)

		return false;

drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c

+1 −1
Original line number Diff line number Diff line
@@ -961,7 +961,7 @@ bool dcn_validate_bandwidth( 
		v->dcc_rate[input_idx] = 1; /*TODO: Worst case? does this change?*/

		v->output_format[input_idx] = pipe->stream->timing.pixel_encoding ==

				PIXEL_ENCODING_YCBCR420 ? dcn_bw_420 : dcn_bw_444;

		v->output[input_idx] = pipe->stream->sink->sink_signal ==

		v->output[input_idx] = pipe->stream->signal ==

				SIGNAL_TYPE_HDMI_TYPE_A ? dcn_bw_hdmi : dcn_bw_dp;

		v->output_deep_color[input_idx] = dcn_bw_encoder_8bpc;

		if (v->output[input_idx] == dcn_bw_hdmi) {

drivers/gpu/drm/amd/display/dc/core/dc.c

+5 −6
Original line number Diff line number Diff line
@@ -384,7 +384,7 @@ void dc_stream_set_dither_option(struct dc_stream_state *stream, 
		enum dc_dither_option option)

{

	struct bit_depth_reduction_params params;

	struct dc_link *link = stream->sink->link;

	struct dc_link *link = stream->link;

	struct pipe_ctx *pipes = NULL;

	int i;
@@ -526,9 +526,8 @@ void dc_link_set_preferred_link_settings(struct dc *dc, 


	for (i = 0; i < MAX_PIPES; i++) {

		pipe = &dc->current_state->res_ctx.pipe_ctx[i];

		if (pipe->stream && pipe->stream->sink

			&& pipe->stream->sink->link) {

			if (pipe->stream->sink->link == link)

		if (pipe->stream && pipe->stream->link) {

			if (pipe->stream->link == link)

				break;

		}

	}
@@ -1045,7 +1044,7 @@ static enum dc_status dc_commit_state_no_check(struct dc *dc, struct dc_state *c 


	/* Program all planes within new context*/

	for (i = 0; i < context->stream_count; i++) {

		const struct dc_sink *sink = context->streams[i]->sink;

		const struct dc_link *link = context->streams[i]->link;



		if (!context->streams[i]->mode_changed)

			continue;
@@ -1070,7 +1069,7 @@ static enum dc_status dc_commit_state_no_check(struct dc *dc, struct dc_state *c 
			}

		}



		CONN_MSG_MODE(sink->link, "{%dx%d, %dx%d@%dKhz}",

		CONN_MSG_MODE(link, "{%dx%d, %dx%d@%dKhz}",

				context->streams[i]->timing.h_addressable,

				context->streams[i]->timing.v_addressable,

				context->streams[i]->timing.h_total,

drivers/gpu/drm/amd/display/dc/core/dc_link.c

+27 −27
Original line number Diff line number Diff line
@@ -789,7 +789,7 @@ bool dc_link_detect(struct dc_link *link, enum dc_detect_reason reason) 
			return false;

		}



		sink->dongle_max_pix_clk = sink_caps.max_hdmi_pixel_clock;

		sink->link->dongle_max_pix_clk = sink_caps.max_hdmi_pixel_clock;

		sink->converter_disable_audio = converter_disable_audio;



		link->local_sink = sink;
@@ -1372,7 +1372,7 @@ static void dpcd_configure_panel_mode( 
static void enable_stream_features(struct pipe_ctx *pipe_ctx)

{

	struct dc_stream_state *stream = pipe_ctx->stream;

	struct dc_link *link = stream->sink->link;

	struct dc_link *link = stream->link;

	union down_spread_ctrl old_downspread;

	union down_spread_ctrl new_downspread;
@@ -1397,7 +1397,7 @@ static enum dc_status enable_link_dp( 
	struct dc_stream_state *stream = pipe_ctx->stream;

	enum dc_status status;

	bool skip_video_pattern;

	struct dc_link *link = stream->sink->link;

	struct dc_link *link = stream->link;

	struct dc_link_settings link_settings = {0};

	enum dp_panel_mode panel_mode;
@@ -1414,8 +1414,8 @@ static enum dc_status enable_link_dp( 
		pipe_ctx->clock_source->id,

		&link_settings);



	if (stream->sink->edid_caps.panel_patch.dppowerup_delay > 0) {

		int delay_dp_power_up_in_ms = stream->sink->edid_caps.panel_patch.dppowerup_delay;

	if (stream->sink_patches.dppowerup_delay > 0) {

		int delay_dp_power_up_in_ms = stream->sink_patches.dppowerup_delay;



		msleep(delay_dp_power_up_in_ms);

	}
@@ -1448,7 +1448,7 @@ static enum dc_status enable_link_edp( 
{

	enum dc_status status;

	struct dc_stream_state *stream = pipe_ctx->stream;

	struct dc_link *link = stream->sink->link;

	struct dc_link *link = stream->link;

	/*in case it is not on*/

	link->dc->hwss.edp_power_control(link, true);

	link->dc->hwss.edp_wait_for_hpd_ready(link, true);
@@ -1463,7 +1463,7 @@ static enum dc_status enable_link_dp_mst( 
		struct dc_state *state,

		struct pipe_ctx *pipe_ctx)

{

	struct dc_link *link = pipe_ctx->stream->sink->link;

	struct dc_link *link = pipe_ctx->stream->link;



	/* sink signal type after MST branch is MST. Multiple MST sinks

	 * share one link. Link DP PHY is enable or training only once.
@@ -1597,7 +1597,7 @@ static bool i2c_write(struct pipe_ctx *pipe_ctx, 
	cmd.payloads = &payload;



	if (dm_helpers_submit_i2c(pipe_ctx->stream->ctx,

			pipe_ctx->stream->sink->link, &cmd))

			pipe_ctx->stream->link, &cmd))

		return true;



	return false;
@@ -1651,7 +1651,7 @@ static void write_i2c_retimer_setting( 
				else {

					i2c_success =

						dal_ddc_service_query_ddc_data(

						pipe_ctx->stream->sink->link->ddc,

						pipe_ctx->stream->link->ddc,

						slave_address, &offset, 1, &value, 1);

					if (!i2c_success)

						/* Write failure */
@@ -1704,7 +1704,7 @@ static void write_i2c_retimer_setting( 
					else {

						i2c_success =

								dal_ddc_service_query_ddc_data(

								pipe_ctx->stream->sink->link->ddc,

								pipe_ctx->stream->link->ddc,

								slave_address, &offset, 1, &value, 1);

						if (!i2c_success)

							/* Write failure */
@@ -1929,7 +1929,7 @@ static void write_i2c_redriver_setting( 
static void enable_link_hdmi(struct pipe_ctx *pipe_ctx)

{

	struct dc_stream_state *stream = pipe_ctx->stream;

	struct dc_link *link = stream->sink->link;

	struct dc_link *link = stream->link;

	enum dc_color_depth display_color_depth;

	enum engine_id eng_id;

	struct ext_hdmi_settings settings = {0};
@@ -1943,7 +1943,7 @@ static void enable_link_hdmi(struct pipe_ctx *pipe_ctx) 
		is_over_340mhz = true;



	if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) {

		unsigned short masked_chip_caps = pipe_ctx->stream->sink->link->chip_caps &

		unsigned short masked_chip_caps = pipe_ctx->stream->link->chip_caps &

				EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK;

		if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_TISN65DP159RSBT) {

			/* DP159, Retimer settings */
@@ -1964,11 +1964,11 @@ static void enable_link_hdmi(struct pipe_ctx *pipe_ctx) 


	if (dc_is_hdmi_signal(pipe_ctx->stream->signal))

		dal_ddc_service_write_scdc_data(

			stream->sink->link->ddc,

			stream->link->ddc,

			stream->phy_pix_clk,

			stream->timing.flags.LTE_340MCSC_SCRAMBLE);



	memset(&stream->sink->link->cur_link_settings, 0,

	memset(&stream->link->cur_link_settings, 0,

			sizeof(struct dc_link_settings));



	display_color_depth = stream->timing.display_color_depth;
@@ -1989,12 +1989,12 @@ static void enable_link_hdmi(struct pipe_ctx *pipe_ctx) 
static void enable_link_lvds(struct pipe_ctx *pipe_ctx)

{

	struct dc_stream_state *stream = pipe_ctx->stream;

	struct dc_link *link = stream->sink->link;

	struct dc_link *link = stream->link;



	if (stream->phy_pix_clk == 0)

		stream->phy_pix_clk = stream->timing.pix_clk_khz;



	memset(&stream->sink->link->cur_link_settings, 0,

	memset(&stream->link->cur_link_settings, 0,

			sizeof(struct dc_link_settings));



	link->link_enc->funcs->enable_lvds_output(
@@ -2145,7 +2145,7 @@ enum dc_status dc_link_validate_mode_timing( 
		struct dc_link *link,

		const struct dc_crtc_timing *timing)

{

	uint32_t max_pix_clk = stream->sink->dongle_max_pix_clk;

	uint32_t max_pix_clk = stream->link->dongle_max_pix_clk;

	struct dpcd_caps *dpcd_caps = &link->dpcd_caps;



	/* A hack to avoid failing any modes for EDID override feature on
@@ -2219,7 +2219,7 @@ bool dc_link_set_backlight_level(const struct dc_link *link, 
		for (i = 0; i < MAX_PIPES; i++) {

			if (core_dc->current_state->res_ctx.pipe_ctx[i].stream) {

				if (core_dc->current_state->res_ctx.

						pipe_ctx[i].stream->sink->link

						pipe_ctx[i].stream->link

						== link)

					/* DMCU -1 for all controller id values,

					 * therefore +1 here
@@ -2279,7 +2279,7 @@ void core_link_resume(struct dc_link *link) 
static struct fixed31_32 get_pbn_per_slot(struct dc_stream_state *stream)

{

	struct dc_link_settings *link_settings =

			&stream->sink->link->cur_link_settings;

			&stream->link->cur_link_settings;

	uint32_t link_rate_in_mbps =

			link_settings->link_rate * LINK_RATE_REF_FREQ_IN_MHZ;

	struct fixed31_32 mbps = dc_fixpt_from_int(
@@ -2386,7 +2386,7 @@ static void update_mst_stream_alloc_table( 
static enum dc_status allocate_mst_payload(struct pipe_ctx *pipe_ctx)

{

	struct dc_stream_state *stream = pipe_ctx->stream;

	struct dc_link *link = stream->sink->link;

	struct dc_link *link = stream->link;

	struct link_encoder *link_encoder = link->link_enc;

	struct stream_encoder *stream_encoder = pipe_ctx->stream_res.stream_enc;

	struct dp_mst_stream_allocation_table proposed_table = {0};
@@ -2466,7 +2466,7 @@ static enum dc_status allocate_mst_payload(struct pipe_ctx *pipe_ctx) 
static enum dc_status deallocate_mst_payload(struct pipe_ctx *pipe_ctx)

{

	struct dc_stream_state *stream = pipe_ctx->stream;

	struct dc_link *link = stream->sink->link;

	struct dc_link *link = stream->link;

	struct link_encoder *link_encoder = link->link_enc;

	struct stream_encoder *stream_encoder = pipe_ctx->stream_res.stream_enc;

	struct dp_mst_stream_allocation_table proposed_table = {0};
@@ -2551,8 +2551,8 @@ void core_link_enable_stream( 
	DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);



	if (pipe_ctx->stream->signal != SIGNAL_TYPE_VIRTUAL) {

		stream->sink->link->link_enc->funcs->setup(

			stream->sink->link->link_enc,

		stream->link->link_enc->funcs->setup(

			stream->link->link_enc,

			pipe_ctx->stream->signal);

		pipe_ctx->stream_res.stream_enc->funcs->setup_stereo_sync(

			pipe_ctx->stream_res.stream_enc,
@@ -2604,7 +2604,7 @@ void core_link_enable_stream( 


		if (status != DC_OK) {

			DC_LOG_WARNING("enabling link %u failed: %d\n",

			pipe_ctx->stream->sink->link->link_index,

			pipe_ctx->stream->link->link_index,

			status);



			/* Abort stream enable *unless* the failure was due to
@@ -2633,12 +2633,12 @@ void core_link_enable_stream( 
			allocate_mst_payload(pipe_ctx);



		core_dc->hwss.unblank_stream(pipe_ctx,

			&pipe_ctx->stream->sink->link->cur_link_settings);

			&pipe_ctx->stream->link->cur_link_settings);



		if (dc_is_dp_signal(pipe_ctx->stream->signal))

			enable_stream_features(pipe_ctx);



		dc_link_set_backlight_level(pipe_ctx->stream->sink->link,

		dc_link_set_backlight_level(pipe_ctx->stream->link,

				pipe_ctx->stream->bl_pwm_level,

				0,

				pipe_ctx->stream);
@@ -2657,7 +2657,7 @@ void core_link_disable_stream(struct pipe_ctx *pipe_ctx, int option) 


	core_dc->hwss.disable_stream(pipe_ctx, option);



	disable_link(pipe_ctx->stream->sink->link, pipe_ctx->stream->signal);

	disable_link(pipe_ctx->stream->link, pipe_ctx->stream->signal);

}



void core_link_set_avmute(struct pipe_ctx *pipe_ctx, bool enable)

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