Commit ce9c13f3 authored by Qi Liu's avatar Qi Liu Committed by Arnaldo Carvalho de Melo
Browse files

perf stat: Fix the ratio comments of miss-events 



'perf stat' displays miss ratio of L1-dcache, L1-icache, dTLB cache,
iTLB cache and LL-cache. Take L1-dcache for example, miss ratio is
caculated as "L1-dcache-load-misses/L1-dcache-loads". So "of all
L1-dcache hits" is unsuitable to describe it, and "of all L1-dcache
accesses" seems better.

The comments of L1-icache, dTLB cache, iTLB cache and LL-cache are
fixed in the same way.

Signed-off-by: default avatarQi Liu <liuqi115@huawei.com>
Reviewed-by: default avatarAndi Kleen <ak@linux.intel.com>
Cc: linuxarm@huawei.com
Link: http://lore.kernel.org/lkml/1600253331-10535-1-git-send-email-liuqi115@huawei.com


Signed-off-by: default avatarArnaldo Carvalho de Melo <acme@redhat.com>
parent d26383dc

tools/perf/util/stat-shadow.c

+10 −10
Original line number Diff line number Diff line
@@ -517,7 +517,7 @@ static void print_l1_dcache_misses(struct perf_stat_config *config, 


	color = get_ratio_color(GRC_CACHE_MISSES, ratio);



	out->print_metric(config, out->ctx, color, "%7.2f%%", "of all L1-dcache hits", ratio);

	out->print_metric(config, out->ctx, color, "%7.2f%%", "of all L1-dcache accesses", ratio);

}



static void print_l1_icache_misses(struct perf_stat_config *config,
@@ -538,7 +538,7 @@ static void print_l1_icache_misses(struct perf_stat_config *config, 
		ratio = avg / total * 100.0;



	color = get_ratio_color(GRC_CACHE_MISSES, ratio);

	out->print_metric(config, out->ctx, color, "%7.2f%%", "of all L1-icache hits", ratio);

	out->print_metric(config, out->ctx, color, "%7.2f%%", "of all L1-icache accesses", ratio);

}



static void print_dtlb_cache_misses(struct perf_stat_config *config,
@@ -558,7 +558,7 @@ static void print_dtlb_cache_misses(struct perf_stat_config *config, 
		ratio = avg / total * 100.0;



	color = get_ratio_color(GRC_CACHE_MISSES, ratio);

	out->print_metric(config, out->ctx, color, "%7.2f%%", "of all dTLB cache hits", ratio);

	out->print_metric(config, out->ctx, color, "%7.2f%%", "of all dTLB cache accesses", ratio);

}



static void print_itlb_cache_misses(struct perf_stat_config *config,
@@ -578,7 +578,7 @@ static void print_itlb_cache_misses(struct perf_stat_config *config, 
		ratio = avg / total * 100.0;



	color = get_ratio_color(GRC_CACHE_MISSES, ratio);

	out->print_metric(config, out->ctx, color, "%7.2f%%", "of all iTLB cache hits", ratio);

	out->print_metric(config, out->ctx, color, "%7.2f%%", "of all iTLB cache accesses", ratio);

}



static void print_ll_cache_misses(struct perf_stat_config *config,
@@ -598,7 +598,7 @@ static void print_ll_cache_misses(struct perf_stat_config *config, 
		ratio = avg / total * 100.0;



	color = get_ratio_color(GRC_CACHE_MISSES, ratio);

	out->print_metric(config, out->ctx, color, "%7.2f%%", "of all LL-cache hits", ratio);

	out->print_metric(config, out->ctx, color, "%7.2f%%", "of all LL-cache accesses", ratio);

}



/*
@@ -920,7 +920,7 @@ void perf_stat__print_shadow_stats(struct perf_stat_config *config, 
		if (runtime_stat_n(st, STAT_L1_DCACHE, ctx, cpu) != 0)

			print_l1_dcache_misses(config, cpu, evsel, avg, out, st);

		else

			print_metric(config, ctxp, NULL, NULL, "of all L1-dcache hits", 0);

			print_metric(config, ctxp, NULL, NULL, "of all L1-dcache accesses", 0);

	} else if (

		evsel->core.attr.type == PERF_TYPE_HW_CACHE &&

		evsel->core.attr.config ==  ( PERF_COUNT_HW_CACHE_L1I |
@@ -930,7 +930,7 @@ void perf_stat__print_shadow_stats(struct perf_stat_config *config, 
		if (runtime_stat_n(st, STAT_L1_ICACHE, ctx, cpu) != 0)

			print_l1_icache_misses(config, cpu, evsel, avg, out, st);

		else

			print_metric(config, ctxp, NULL, NULL, "of all L1-icache hits", 0);

			print_metric(config, ctxp, NULL, NULL, "of all L1-icache accesses", 0);

	} else if (

		evsel->core.attr.type == PERF_TYPE_HW_CACHE &&

		evsel->core.attr.config ==  ( PERF_COUNT_HW_CACHE_DTLB |
@@ -940,7 +940,7 @@ void perf_stat__print_shadow_stats(struct perf_stat_config *config, 
		if (runtime_stat_n(st, STAT_DTLB_CACHE, ctx, cpu) != 0)

			print_dtlb_cache_misses(config, cpu, evsel, avg, out, st);

		else

			print_metric(config, ctxp, NULL, NULL, "of all dTLB cache hits", 0);

			print_metric(config, ctxp, NULL, NULL, "of all dTLB cache accesses", 0);

	} else if (

		evsel->core.attr.type == PERF_TYPE_HW_CACHE &&

		evsel->core.attr.config ==  ( PERF_COUNT_HW_CACHE_ITLB |
@@ -950,7 +950,7 @@ void perf_stat__print_shadow_stats(struct perf_stat_config *config, 
		if (runtime_stat_n(st, STAT_ITLB_CACHE, ctx, cpu) != 0)

			print_itlb_cache_misses(config, cpu, evsel, avg, out, st);

		else

			print_metric(config, ctxp, NULL, NULL, "of all iTLB cache hits", 0);

			print_metric(config, ctxp, NULL, NULL, "of all iTLB cache accesses", 0);

	} else if (

		evsel->core.attr.type == PERF_TYPE_HW_CACHE &&

		evsel->core.attr.config ==  ( PERF_COUNT_HW_CACHE_LL |
@@ -960,7 +960,7 @@ void perf_stat__print_shadow_stats(struct perf_stat_config *config, 
		if (runtime_stat_n(st, STAT_LL_CACHE, ctx, cpu) != 0)

			print_ll_cache_misses(config, cpu, evsel, avg, out, st);

		else

			print_metric(config, ctxp, NULL, NULL, "of all LL-cache hits", 0);

			print_metric(config, ctxp, NULL, NULL, "of all LL-cache accesses", 0);

	} else if (evsel__match(evsel, HARDWARE, HW_CACHE_MISSES)) {

		total = runtime_stat_avg(st, STAT_CACHEREFS, ctx, cpu);

CRA Git | Maintained and supported by SUSTech CRA and CCSE