Commit ce8c2293 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'master' of master.kernel.org:/pub/scm/linux/kernel/git/davem/net-2.6 

* 'master' of master.kernel.org:/pub/scm/linux/kernel/git/davem/net-2.6: (25 commits)
  [TG3]: Fix msi issue with kexec/kdump.
  [NET] XFRM: Fix whitespace errors.
  [NET] TIPC: Fix whitespace errors.
  [NET] SUNRPC: Fix whitespace errors.
  [NET] SCTP: Fix whitespace errors.
  [NET] RXRPC: Fix whitespace errors.
  [NET] ROSE: Fix whitespace errors.
  [NET] RFKILL: Fix whitespace errors.
  [NET] PACKET: Fix whitespace errors.
  [NET] NETROM: Fix whitespace errors.
  [NET] NETFILTER: Fix whitespace errors.
  [NET] IPV4: Fix whitespace errors.
  [NET] DCCP: Fix whitespace errors.
  [NET] CORE: Fix whitespace errors.
  [NET] BLUETOOTH: Fix whitespace errors.
  [NET] AX25: Fix whitespace errors.
  [PATCH] mac80211: remove rtnl locking in ieee80211_sta.c
  [PATCH] mac80211: fix GCC warning on 64bit platforms
  [GENETLINK]: Dynamic multicast groups.
  [NETLIKN]: Allow removing multicast groups.
  ...
parents 41e9d344 ee6a99b5

drivers/net/tg3.c

+65 −49
Original line number Diff line number Diff line
@@ -64,8 +64,8 @@ 


#define DRV_MODULE_NAME		"tg3"

#define PFX DRV_MODULE_NAME	": "

#define DRV_MODULE_VERSION	"3.78"

#define DRV_MODULE_RELDATE	"July 11, 2007"

#define DRV_MODULE_VERSION	"3.79"

#define DRV_MODULE_RELDATE	"July 18, 2007"



#define TG3_DEF_MAC_MODE	0

#define TG3_DEF_RX_MODE		0
@@ -4847,6 +4847,59 @@ static int tg3_poll_fw(struct tg3 *tp) 
	return 0;

}



/* Save PCI command register before chip reset */

static void tg3_save_pci_state(struct tg3 *tp)

{

	u32 val;



	pci_read_config_dword(tp->pdev, TG3PCI_COMMAND, &val);

	tp->pci_cmd = val;

}



/* Restore PCI state after chip reset */

static void tg3_restore_pci_state(struct tg3 *tp)

{

	u32 val;



	/* Re-enable indirect register accesses. */

	pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,

			       tp->misc_host_ctrl);



	/* Set MAX PCI retry to zero. */

	val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);

	if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&

	    (tp->tg3_flags & TG3_FLAG_PCIX_MODE))

		val |= PCISTATE_RETRY_SAME_DMA;

	pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);



	pci_write_config_dword(tp->pdev, TG3PCI_COMMAND, tp->pci_cmd);



	/* Make sure PCI-X relaxed ordering bit is clear. */

	pci_read_config_dword(tp->pdev, TG3PCI_X_CAPS, &val);

	val &= ~PCIX_CAPS_RELAXED_ORDERING;

	pci_write_config_dword(tp->pdev, TG3PCI_X_CAPS, val);



	if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {

		u32 val;



		/* Chip reset on 5780 will reset MSI enable bit,

		 * so need to restore it.

		 */

		if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {

			u16 ctrl;



			pci_read_config_word(tp->pdev,

					     tp->msi_cap + PCI_MSI_FLAGS,

					     &ctrl);

			pci_write_config_word(tp->pdev,

					      tp->msi_cap + PCI_MSI_FLAGS,

					      ctrl | PCI_MSI_FLAGS_ENABLE);

			val = tr32(MSGINT_MODE);

			tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);

		}

	}

}



static void tg3_stop_fw(struct tg3 *);



/* tp->lock is held. */
@@ -4863,6 +4916,12 @@ static int tg3_chip_reset(struct tg3 *tp) 
	 */

	tp->nvram_lock_cnt = 0;



	/* GRC_MISC_CFG core clock reset will clear the memory

	 * enable bit in PCI register 4 and the MSI enable bit

	 * on some chips, so we save relevant registers here.

	 */

	tg3_save_pci_state(tp);



	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||

	    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||

	    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
@@ -4961,51 +5020,15 @@ static int tg3_chip_reset(struct tg3 *tp) 
		pci_write_config_dword(tp->pdev, 0xd8, 0xf5000);

	}



	/* Re-enable indirect register accesses. */

	pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,

			       tp->misc_host_ctrl);



	/* Set MAX PCI retry to zero. */

	val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);

	if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&

	    (tp->tg3_flags & TG3_FLAG_PCIX_MODE))

		val |= PCISTATE_RETRY_SAME_DMA;

	pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);



	pci_restore_state(tp->pdev);

	tg3_restore_pci_state(tp);



	tp->tg3_flags &= ~TG3_FLAG_CHIP_RESETTING;



	/* Make sure PCI-X relaxed ordering bit is clear. */

	pci_read_config_dword(tp->pdev, TG3PCI_X_CAPS, &val);

	val &= ~PCIX_CAPS_RELAXED_ORDERING;

	pci_write_config_dword(tp->pdev, TG3PCI_X_CAPS, val);



	if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {

		u32 val;



		/* Chip reset on 5780 will reset MSI enable bit,

		 * so need to restore it.

		 */

		if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {

			u16 ctrl;



			pci_read_config_word(tp->pdev,

					     tp->msi_cap + PCI_MSI_FLAGS,

					     &ctrl);

			pci_write_config_word(tp->pdev,

					      tp->msi_cap + PCI_MSI_FLAGS,

					      ctrl | PCI_MSI_FLAGS_ENABLE);

			val = tr32(MSGINT_MODE);

			tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);

		}



	val = 0;

	if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)

		val = tr32(MEMARB_MODE);

	tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);



	} else

		tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);



	if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {

		tg3_stop_fw(tp);

		tw32(0x5000, 0x400);
@@ -11978,7 +12001,6 @@ static int __devinit tg3_init_one(struct pci_dev *pdev, 
	 */

	if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||

	    (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {

		pci_save_state(tp->pdev);

		tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);

		tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);

	}
@@ -12007,12 +12029,6 @@ static int __devinit tg3_init_one(struct pci_dev *pdev, 


	tg3_init_coal(tp);



	/* Now that we have fully setup the chip, save away a snapshot

	 * of the PCI config space.  We need to restore this after

	 * GRC_MISC_CFG core clock resets and some resume events.

	 */

	pci_save_state(tp->pdev);



	pci_set_drvdata(pdev, dev);



	err = register_netdev(dev);

drivers/net/tg3.h

+1 −0
Original line number Diff line number Diff line
@@ -2345,6 +2345,7 @@ struct tg3 { 
#define PHY_REV_BCM5411_X0		0x1 /* Found on Netgear GA302T */



	u32				led_ctrl;

	u32				pci_cmd;



	char				board_part_number[24];

	char				fw_ver[16];

include/linux/genetlink.h

+13 −0
Original line number Diff line number Diff line
@@ -39,6 +39,9 @@ enum { 
	CTRL_CMD_NEWOPS,

	CTRL_CMD_DELOPS,

	CTRL_CMD_GETOPS,

	CTRL_CMD_NEWMCAST_GRP,

	CTRL_CMD_DELMCAST_GRP,

	CTRL_CMD_GETMCAST_GRP, /* unused */

	__CTRL_CMD_MAX,

};
@@ -52,6 +55,7 @@ enum { 
	CTRL_ATTR_HDRSIZE,

	CTRL_ATTR_MAXATTR,

	CTRL_ATTR_OPS,

	CTRL_ATTR_MCAST_GROUPS,

	__CTRL_ATTR_MAX,

};
@@ -66,4 +70,13 @@ enum { 


#define CTRL_ATTR_OP_MAX (__CTRL_ATTR_OP_MAX - 1)



enum {

	CTRL_ATTR_MCAST_GRP_UNSPEC,

	CTRL_ATTR_MCAST_GRP_NAME,

	CTRL_ATTR_MCAST_GRP_ID,

	__CTRL_ATTR_MCAST_GRP_MAX,

};



#define CTRL_ATTR_MCAST_GRP_MAX (__CTRL_ATTR_MCAST_GRP_MAX - 1)



#endif	/* __LINUX_GENERIC_NETLINK_H */

include/linux/netlink.h

+2 −0
Original line number Diff line number Diff line
@@ -161,6 +161,8 @@ extern struct sock *netlink_kernel_create(int unit, unsigned int groups, 
					  void (*input)(struct sock *sk, int len),

					  struct mutex *cb_mutex,

					  struct module *module);

extern int netlink_change_ngroups(struct sock *sk, unsigned int groups);

extern void netlink_clear_multicast_users(struct sock *sk, unsigned int group);

extern void netlink_ack(struct sk_buff *in_skb, struct nlmsghdr *nlh, int err);

extern int netlink_has_listeners(struct sock *sk, unsigned int group);

extern int netlink_unicast(struct sock *ssk, struct sk_buff *skb, __u32 pid, int nonblock);

include/net/genetlink.h

+22 −0
Original line number Diff line number Diff line
@@ -4,6 +4,22 @@ 
#include <linux/genetlink.h>

#include <net/netlink.h>



/**

 * struct genl_multicast_group - generic netlink multicast group

 * @name: name of the multicast group, names are per-family

 * @id: multicast group ID, assigned by the core, to use with

 *      genlmsg_multicast().

 * @list: list entry for linking

 * @family: pointer to family, need not be set before registering

 */

struct genl_multicast_group

{

	struct genl_family	*family;	/* private */

	struct list_head	list;		/* private */

	char			name[GENL_NAMSIZ];

	u32			id;

};



/**

 * struct genl_family - generic netlink family

 * @id: protocol family idenfitier
@@ -14,6 +30,7 @@ 
 * @attrbuf: buffer to store parsed attributes

 * @ops_list: list of all assigned operations

 * @family_list: family list

 * @mcast_groups: multicast groups list

 */

struct genl_family

{
@@ -25,6 +42,7 @@ struct genl_family 
	struct nlattr **	attrbuf;	/* private */

	struct list_head	ops_list;	/* private */

	struct list_head	family_list;	/* private */

	struct list_head	mcast_groups;	/* private */

};



/**
@@ -73,6 +91,10 @@ extern int genl_register_family(struct genl_family *family); 
extern int genl_unregister_family(struct genl_family *family);

extern int genl_register_ops(struct genl_family *, struct genl_ops *ops);

extern int genl_unregister_ops(struct genl_family *, struct genl_ops *ops);

extern int genl_register_mc_group(struct genl_family *family,

				  struct genl_multicast_group *grp);

extern void genl_unregister_mc_group(struct genl_family *family,

				     struct genl_multicast_group *grp);



extern struct sock *genl_sock;

CRA Git | Maintained and supported by SUSTech CRA and CCSE