Commit ce8672c2 authored by Linus Walleij's avatar Linus Walleij
Browse files

Merge tag 'intel-gpio-v5.9-1' of... 

Merge tag 'intel-gpio-v5.9-1' of git://git.kernel.org/pub/scm/linux/kernel/git/andy/linux-gpio-intel into devel

intel-gpio for v5.9-1

* Move GPIO PMIC drivers to use IRQ chip template
* Introduce for_each_requested_gpio() and convert existing users
* Replace unsigned by unsigned int in few drivers
* Fix an issue in kernel doc that validator complains about
* Move to verbose debug level the IRQ status message in gpio-pch

The following is an automated git shortlog grouped by driver:

ARM/orion/gpio:
 -  Make use of for_each_requested_gpio()

crystalcove:
 -  Use irqchip template
 -  changed every 'unsigned' to 'unsigned int'

gpiolib:
 -  Introduce for_each_requested_gpio_in_range() macro

gpio-ml-ioh:
 -  Fix missing ':' in 'struct ioh_gpio_reg_data

ich:
 -  changed every 'unsigned' to 'unsigned int'

mvebu:
 -  Make use of for_each_requested_gpio()

pch:
 -  Add a blank line between declaration and code
 -  changed every 'unsigned' to 'unsigned int'
 -  Move IRQ status message to verbose debug level

pinctrl:
 -  at91: Make use of for_each_requested_gpio()

sch:
 -  Add a blank line between declaration and code
 -  changed every 'unsigned' to 'unsigned int'

wcove:
 -  Use irqchip template

xra1403:
 -  Make use of for_each_requested_gpio()
parents edee3bc6 4941b8de

drivers/gpio/gpio-crystalcove.c

+20 −14
Original line number Diff line number Diff line
@@ -129,7 +129,7 @@ static void crystalcove_update_irq_ctrl(struct crystalcove_gpio *cg, int gpio) 
	regmap_update_bits(cg->regmap, reg, CTLI_INTCNT_BE, cg->intcnt_value);

}



static int crystalcove_gpio_dir_in(struct gpio_chip *chip, unsigned gpio)

static int crystalcove_gpio_dir_in(struct gpio_chip *chip, unsigned int gpio)

{

	struct crystalcove_gpio *cg = gpiochip_get_data(chip);

	int reg = to_reg(gpio, CTRL_OUT);
@@ -140,7 +140,7 @@ static int crystalcove_gpio_dir_in(struct gpio_chip *chip, unsigned gpio) 
	return regmap_write(cg->regmap, reg, CTLO_INPUT_SET);

}



static int crystalcove_gpio_dir_out(struct gpio_chip *chip, unsigned gpio,

static int crystalcove_gpio_dir_out(struct gpio_chip *chip, unsigned int gpio,

				    int value)

{

	struct crystalcove_gpio *cg = gpiochip_get_data(chip);
@@ -152,7 +152,7 @@ static int crystalcove_gpio_dir_out(struct gpio_chip *chip, unsigned gpio, 
	return regmap_write(cg->regmap, reg, CTLO_OUTPUT_SET | value);

}



static int crystalcove_gpio_get(struct gpio_chip *chip, unsigned gpio)

static int crystalcove_gpio_get(struct gpio_chip *chip, unsigned int gpio)

{

	struct crystalcove_gpio *cg = gpiochip_get_data(chip);

	unsigned int val;
@@ -169,7 +169,7 @@ static int crystalcove_gpio_get(struct gpio_chip *chip, unsigned gpio) 
}



static void crystalcove_gpio_set(struct gpio_chip *chip,

				 unsigned gpio, int value)

				 unsigned int gpio, int value)

{

	struct crystalcove_gpio *cg = gpiochip_get_data(chip);

	int reg = to_reg(gpio, CTRL_OUT);
@@ -183,7 +183,7 @@ static void crystalcove_gpio_set(struct gpio_chip *chip, 
		regmap_update_bits(cg->regmap, reg, 1, 0);

}



static int crystalcove_irq_type(struct irq_data *data, unsigned type)

static int crystalcove_irq_type(struct irq_data *data, unsigned int type)

{

	struct crystalcove_gpio *cg =

		gpiochip_get_data(irq_data_get_irq_chip_data(data));
@@ -330,6 +330,7 @@ static int crystalcove_gpio_probe(struct platform_device *pdev) 
	int retval;

	struct device *dev = pdev->dev.parent;

	struct intel_soc_pmic *pmic = dev_get_drvdata(dev);

	struct gpio_irq_chip *girq;



	if (irq < 0)

		return irq;
@@ -353,14 +354,15 @@ static int crystalcove_gpio_probe(struct platform_device *pdev) 
	cg->chip.dbg_show = crystalcove_gpio_dbg_show;

	cg->regmap = pmic->regmap;



	retval = devm_gpiochip_add_data(&pdev->dev, &cg->chip, cg);

	if (retval) {

		dev_warn(&pdev->dev, "add gpio chip error: %d\n", retval);

		return retval;

	}



	gpiochip_irqchip_add_nested(&cg->chip, &crystalcove_irqchip, 0,

				    handle_simple_irq, IRQ_TYPE_NONE);

	girq = &cg->chip.irq;

	girq->chip = &crystalcove_irqchip;

	/* This will let us handle the parent IRQ in the driver */

	girq->parent_handler = NULL;

	girq->num_parents = 0;

	girq->parents = NULL;

	girq->default_type = IRQ_TYPE_NONE;

	girq->handler = handle_simple_irq;

	girq->threaded = true;



	retval = request_threaded_irq(irq, NULL, crystalcove_gpio_irq_handler,

				      IRQF_ONESHOT, KBUILD_MODNAME, cg);
@@ -370,7 +372,11 @@ static int crystalcove_gpio_probe(struct platform_device *pdev) 
		return retval;

	}



	gpiochip_set_nested_irqchip(&cg->chip, &crystalcove_irqchip, irq);

	retval = devm_gpiochip_add_data(&pdev->dev, &cg->chip, cg);

	if (retval) {

		dev_warn(&pdev->dev, "add gpio chip error: %d\n", retval);

		return retval;

	}



	return 0;

}

drivers/gpio/gpio-ich.c

+13 −13
Original line number Diff line number Diff line
@@ -74,8 +74,8 @@ struct ichx_desc { 
	u32 use_sel_ignore[3];



	/* Some chipsets have quirks, let these use their own request/get */

	int (*request)(struct gpio_chip *chip, unsigned offset);

	int (*get)(struct gpio_chip *chip, unsigned offset);

	int (*request)(struct gpio_chip *chip, unsigned int offset);

	int (*get)(struct gpio_chip *chip, unsigned int offset);



	/*

	 * Some chipsets don't let reading output values on GPIO_LVL register
@@ -100,7 +100,7 @@ static int modparam_gpiobase = -1; /* dynamic */ 
module_param_named(gpiobase, modparam_gpiobase, int, 0444);

MODULE_PARM_DESC(gpiobase, "The GPIO number base. -1 means dynamic, which is the default.");



static int ichx_write_bit(int reg, unsigned nr, int val, int verify)

static int ichx_write_bit(int reg, unsigned int nr, int val, int verify)

{

	unsigned long flags;

	u32 data, tmp;
@@ -132,7 +132,7 @@ static int ichx_write_bit(int reg, unsigned nr, int val, int verify) 
	return (verify && data != tmp) ? -EPERM : 0;

}



static int ichx_read_bit(int reg, unsigned nr)

static int ichx_read_bit(int reg, unsigned int nr)

{

	unsigned long flags;

	u32 data;
@@ -152,12 +152,12 @@ static int ichx_read_bit(int reg, unsigned nr) 
	return !!(data & BIT(bit));

}



static bool ichx_gpio_check_available(struct gpio_chip *gpio, unsigned nr)

static bool ichx_gpio_check_available(struct gpio_chip *gpio, unsigned int nr)

{

	return !!(ichx_priv.use_gpio & BIT(nr / 32));

}



static int ichx_gpio_get_direction(struct gpio_chip *gpio, unsigned nr)

static int ichx_gpio_get_direction(struct gpio_chip *gpio, unsigned int nr)

{

	if (ichx_read_bit(GPIO_IO_SEL, nr))

		return GPIO_LINE_DIRECTION_IN;
@@ -165,7 +165,7 @@ static int ichx_gpio_get_direction(struct gpio_chip *gpio, unsigned nr) 
	return GPIO_LINE_DIRECTION_OUT;

}



static int ichx_gpio_direction_input(struct gpio_chip *gpio, unsigned nr)

static int ichx_gpio_direction_input(struct gpio_chip *gpio, unsigned int nr)

{

	/*

	 * Try setting pin as an input and verify it worked since many pins
@@ -174,7 +174,7 @@ static int ichx_gpio_direction_input(struct gpio_chip *gpio, unsigned nr) 
	return ichx_write_bit(GPIO_IO_SEL, nr, 1, 1);

}



static int ichx_gpio_direction_output(struct gpio_chip *gpio, unsigned nr,

static int ichx_gpio_direction_output(struct gpio_chip *gpio, unsigned int nr,

					int val)

{

	/* Disable blink hardware which is available for GPIOs from 0 to 31. */
@@ -191,12 +191,12 @@ static int ichx_gpio_direction_output(struct gpio_chip *gpio, unsigned nr, 
	return ichx_write_bit(GPIO_IO_SEL, nr, 0, 1);

}



static int ichx_gpio_get(struct gpio_chip *chip, unsigned nr)

static int ichx_gpio_get(struct gpio_chip *chip, unsigned int nr)

{

	return ichx_read_bit(GPIO_LVL, nr);

}



static int ich6_gpio_get(struct gpio_chip *chip, unsigned nr)

static int ich6_gpio_get(struct gpio_chip *chip, unsigned int nr)

{

	unsigned long flags;

	u32 data;
@@ -223,7 +223,7 @@ static int ich6_gpio_get(struct gpio_chip *chip, unsigned nr) 
	}

}



static int ichx_gpio_request(struct gpio_chip *chip, unsigned nr)

static int ichx_gpio_request(struct gpio_chip *chip, unsigned int nr)

{

	if (!ichx_gpio_check_available(chip, nr))

		return -ENXIO;
@@ -240,7 +240,7 @@ static int ichx_gpio_request(struct gpio_chip *chip, unsigned nr) 
	return ichx_read_bit(GPIO_USE_SEL, nr) ? 0 : -ENODEV;

}



static int ich6_gpio_request(struct gpio_chip *chip, unsigned nr)

static int ich6_gpio_request(struct gpio_chip *chip, unsigned int nr)

{

	/*

	 * Fixups for bits 16 and 17 are necessary on the Intel ICH6/3100
@@ -254,7 +254,7 @@ static int ich6_gpio_request(struct gpio_chip *chip, unsigned nr) 
	return ichx_gpio_request(chip, nr);

}



static void ichx_gpio_set(struct gpio_chip *chip, unsigned nr, int val)

static void ichx_gpio_set(struct gpio_chip *chip, unsigned int nr, int val)

{

	ichx_write_bit(GPIO_LVL, nr, val, 0);

}

drivers/gpio/gpio-ml-ioh.c

+1 −1
Original line number Diff line number Diff line
@@ -44,7 +44,7 @@ struct ioh_regs { 


/**

 * struct ioh_gpio_reg_data - The register store data.

 * @ien_reg	To store contents of interrupt enable register.

 * @ien_reg:	To store contents of interrupt enable register.

 * @imask_reg:	To store contents of interrupt mask regist

 * @po_reg:	To store contents of PO register.

 * @pm_reg:	To store contents of PM register.

drivers/gpio/gpio-pch.c

+8 −6
Original line number Diff line number Diff line
@@ -95,7 +95,7 @@ struct pch_gpio { 
	spinlock_t spinlock;

};



static void pch_gpio_set(struct gpio_chip *gpio, unsigned nr, int val)

static void pch_gpio_set(struct gpio_chip *gpio, unsigned int nr, int val)

{

	u32 reg_val;

	struct pch_gpio *chip =	gpiochip_get_data(gpio);
@@ -112,14 +112,14 @@ static void pch_gpio_set(struct gpio_chip *gpio, unsigned nr, int val) 
	spin_unlock_irqrestore(&chip->spinlock, flags);

}



static int pch_gpio_get(struct gpio_chip *gpio, unsigned nr)

static int pch_gpio_get(struct gpio_chip *gpio, unsigned int nr)

{

	struct pch_gpio *chip =	gpiochip_get_data(gpio);



	return !!(ioread32(&chip->reg->pi) & BIT(nr));

}



static int pch_gpio_direction_output(struct gpio_chip *gpio, unsigned nr,

static int pch_gpio_direction_output(struct gpio_chip *gpio, unsigned int nr,

				     int val)

{

	struct pch_gpio *chip =	gpiochip_get_data(gpio);
@@ -146,7 +146,7 @@ static int pch_gpio_direction_output(struct gpio_chip *gpio, unsigned nr, 
	return 0;

}



static int pch_gpio_direction_input(struct gpio_chip *gpio, unsigned nr)

static int pch_gpio_direction_input(struct gpio_chip *gpio, unsigned int nr)

{

	struct pch_gpio *chip =	gpiochip_get_data(gpio);

	u32 pm;
@@ -196,9 +196,10 @@ static void __maybe_unused pch_gpio_restore_reg_conf(struct pch_gpio *chip) 
		iowrite32(chip->pch_gpio_reg.gpio_use_sel_reg, &chip->reg->gpio_use_sel);

}



static int pch_gpio_to_irq(struct gpio_chip *gpio, unsigned offset)

static int pch_gpio_to_irq(struct gpio_chip *gpio, unsigned int offset)

{

	struct pch_gpio *chip = gpiochip_get_data(gpio);



	return chip->irq_base + offset;

}
@@ -304,9 +305,10 @@ static irqreturn_t pch_gpio_handler(int irq, void *dev_id) 
	unsigned long reg_val = ioread32(&chip->reg->istatus);

	int i;



	dev_dbg(chip->dev, "irq=%d  status=0x%lx\n", irq, reg_val);

	dev_vdbg(chip->dev, "irq=%d  status=0x%lx\n", irq, reg_val);



	reg_val &= BIT(gpio_pins[chip->ioh]) - 1;



	for_each_set_bit(i, &reg_val, gpio_pins[chip->ioh])

		generic_handle_irq(chip->irq_base + i);

drivers/gpio/gpio-sch.c

+12 −11
Original line number Diff line number Diff line
@@ -26,10 +26,10 @@ struct sch_gpio { 
	unsigned short resume_base;

};



static unsigned sch_gpio_offset(struct sch_gpio *sch, unsigned gpio,

				unsigned reg)

static unsigned int sch_gpio_offset(struct sch_gpio *sch, unsigned int gpio,

				unsigned int reg)

{

	unsigned base = 0;

	unsigned int base = 0;



	if (gpio >= sch->resume_base) {

		gpio -= sch->resume_base;
@@ -39,14 +39,14 @@ static unsigned sch_gpio_offset(struct sch_gpio *sch, unsigned gpio, 
	return base + reg + gpio / 8;

}



static unsigned sch_gpio_bit(struct sch_gpio *sch, unsigned gpio)

static unsigned int sch_gpio_bit(struct sch_gpio *sch, unsigned int gpio)

{

	if (gpio >= sch->resume_base)

		gpio -= sch->resume_base;

	return gpio % 8;

}



static int sch_gpio_reg_get(struct sch_gpio *sch, unsigned gpio, unsigned reg)

static int sch_gpio_reg_get(struct sch_gpio *sch, unsigned int gpio, unsigned int reg)

{

	unsigned short offset, bit;

	u8 reg_val;
@@ -59,7 +59,7 @@ static int sch_gpio_reg_get(struct sch_gpio *sch, unsigned gpio, unsigned reg) 
	return reg_val;

}



static void sch_gpio_reg_set(struct sch_gpio *sch, unsigned gpio, unsigned reg,

static void sch_gpio_reg_set(struct sch_gpio *sch, unsigned int gpio, unsigned int reg,

			     int val)

{

	unsigned short offset, bit;
@@ -76,7 +76,7 @@ static void sch_gpio_reg_set(struct sch_gpio *sch, unsigned gpio, unsigned reg, 
		outb((reg_val & ~BIT(bit)), sch->iobase + offset);

}



static int sch_gpio_direction_in(struct gpio_chip *gc, unsigned gpio_num)

static int sch_gpio_direction_in(struct gpio_chip *gc, unsigned int gpio_num)

{

	struct sch_gpio *sch = gpiochip_get_data(gc);
@@ -86,13 +86,14 @@ static int sch_gpio_direction_in(struct gpio_chip *gc, unsigned gpio_num) 
	return 0;

}



static int sch_gpio_get(struct gpio_chip *gc, unsigned gpio_num)

static int sch_gpio_get(struct gpio_chip *gc, unsigned int gpio_num)

{

	struct sch_gpio *sch = gpiochip_get_data(gc);



	return sch_gpio_reg_get(sch, gpio_num, GLV);

}



static void sch_gpio_set(struct gpio_chip *gc, unsigned gpio_num, int val)

static void sch_gpio_set(struct gpio_chip *gc, unsigned int gpio_num, int val)

{

	struct sch_gpio *sch = gpiochip_get_data(gc);
@@ -101,7 +102,7 @@ static void sch_gpio_set(struct gpio_chip *gc, unsigned gpio_num, int val) 
	spin_unlock(&sch->lock);

}



static int sch_gpio_direction_out(struct gpio_chip *gc, unsigned gpio_num,

static int sch_gpio_direction_out(struct gpio_chip *gc, unsigned int gpio_num,

				  int val)

{

	struct sch_gpio *sch = gpiochip_get_data(gc);
@@ -123,7 +124,7 @@ static int sch_gpio_direction_out(struct gpio_chip *gc, unsigned gpio_num, 
	return 0;

}



static int sch_gpio_get_direction(struct gpio_chip *gc, unsigned gpio_num)

static int sch_gpio_get_direction(struct gpio_chip *gc, unsigned int gpio_num)

{

	struct sch_gpio *sch = gpiochip_get_data(gc);

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