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Add HFLIP/VFLIP controls support by setting registers REG21/REG20. Useless values in hardcoded mode sequences are removed and remaining binning values are now set after mode sequence being set. Note that due to BSI (Back Side Illuminated) technology, image capture is physically mirrored, mirror logic is so inversed in REG21 register to cancel this effect. Signed-off-by:Hugues Fruchet <hugues.fruchet@st.com> Signed-off-by:
Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by:
Mauro Carvalho Chehab <mchehab+samsung@kernel.org>
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