Commit ce65b874 authored by Christian König's avatar Christian König
Browse files

drm/ttm: nuke caching placement flags 



Changing the caching on the fly never really worked
flawlessly.

So stop this completely and just let drivers specific the
desired caching in the tt or bus object.

Signed-off-by: default avatarChristian König <christian.koenig@amd.com>
Reviewed-by: default avatarMichael J. Ruhl <michael.j.ruhl@intel.com>
Link: https://patchwork.freedesktop.org/patch/394256/
parent 867bcecd

drivers/gpu/drm/amd/amdgpu/amdgpu_object.c

+5 −15
Original line number Diff line number Diff line
@@ -137,7 +137,7 @@ void amdgpu_bo_placement_from_domain(struct amdgpu_bo *abo, u32 domain) 
		places[c].fpfn = 0;

		places[c].lpfn = 0;

		places[c].mem_type = TTM_PL_VRAM;

		places[c].flags = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED;

		places[c].flags = 0;



		if (flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED)

			places[c].lpfn = visible_pfn;
@@ -154,11 +154,6 @@ void amdgpu_bo_placement_from_domain(struct amdgpu_bo *abo, u32 domain) 
		places[c].lpfn = 0;

		places[c].mem_type = TTM_PL_TT;

		places[c].flags = 0;

		if (flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC)

			places[c].flags |= TTM_PL_FLAG_WC |

				TTM_PL_FLAG_UNCACHED;

		else

			places[c].flags |= TTM_PL_FLAG_CACHED;

		c++;

	}
@@ -167,11 +162,6 @@ void amdgpu_bo_placement_from_domain(struct amdgpu_bo *abo, u32 domain) 
		places[c].lpfn = 0;

		places[c].mem_type = TTM_PL_SYSTEM;

		places[c].flags = 0;

		if (flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC)

			places[c].flags |= TTM_PL_FLAG_WC |

				TTM_PL_FLAG_UNCACHED;

		else

			places[c].flags |= TTM_PL_FLAG_CACHED;

		c++;

	}
@@ -179,7 +169,7 @@ void amdgpu_bo_placement_from_domain(struct amdgpu_bo *abo, u32 domain) 
		places[c].fpfn = 0;

		places[c].lpfn = 0;

		places[c].mem_type = AMDGPU_PL_GDS;

		places[c].flags = TTM_PL_FLAG_UNCACHED;

		places[c].flags = 0;

		c++;

	}
@@ -187,7 +177,7 @@ void amdgpu_bo_placement_from_domain(struct amdgpu_bo *abo, u32 domain) 
		places[c].fpfn = 0;

		places[c].lpfn = 0;

		places[c].mem_type = AMDGPU_PL_GWS;

		places[c].flags = TTM_PL_FLAG_UNCACHED;

		places[c].flags = 0;

		c++;

	}
@@ -195,7 +185,7 @@ void amdgpu_bo_placement_from_domain(struct amdgpu_bo *abo, u32 domain) 
		places[c].fpfn = 0;

		places[c].lpfn = 0;

		places[c].mem_type = AMDGPU_PL_OA;

		places[c].flags = TTM_PL_FLAG_UNCACHED;

		places[c].flags = 0;

		c++;

	}
@@ -203,7 +193,7 @@ void amdgpu_bo_placement_from_domain(struct amdgpu_bo *abo, u32 domain) 
		places[c].fpfn = 0;

		places[c].lpfn = 0;

		places[c].mem_type = TTM_PL_SYSTEM;

		places[c].flags = TTM_PL_MASK_CACHING;

		places[c].flags = 0;

		c++;

	}

drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c

+3 −9
Original line number Diff line number Diff line
@@ -92,7 +92,7 @@ static void amdgpu_evict_flags(struct ttm_buffer_object *bo, 
		.fpfn = 0,

		.lpfn = 0,

		.mem_type = TTM_PL_SYSTEM,

		.flags = TTM_PL_MASK_CACHING

		.flags = 0

	};



	/* Don't handle scatter gather BOs */
@@ -538,19 +538,13 @@ static int amdgpu_move_vram_ram(struct ttm_buffer_object *bo, bool evict, 
	placements.fpfn = 0;

	placements.lpfn = 0;

	placements.mem_type = TTM_PL_TT;

	placements.flags = TTM_PL_MASK_CACHING;

	placements.flags = 0;

	r = ttm_bo_mem_space(bo, &placement, &tmp_mem, ctx);

	if (unlikely(r)) {

		pr_err("Failed to find GTT space for blit from VRAM\n");

		return r;

	}



	/* set caching flags */

	r = ttm_tt_set_placement_caching(bo->ttm, tmp_mem.placement);

	if (unlikely(r)) {

		goto out_cleanup;

	}



	r = ttm_tt_populate(bo->bdev, bo->ttm, ctx);

	if (unlikely(r))

		goto out_cleanup;
@@ -599,7 +593,7 @@ static int amdgpu_move_ram_vram(struct ttm_buffer_object *bo, bool evict, 
	placements.fpfn = 0;

	placements.lpfn = 0;

	placements.mem_type = TTM_PL_TT;

	placements.flags = TTM_PL_MASK_CACHING;

	placements.flags = 0;

	r = ttm_bo_mem_space(bo, &placement, &tmp_mem, ctx);

	if (unlikely(r)) {

		pr_err("Failed to find GTT space for blit to VRAM\n");

drivers/gpu/drm/drm_gem_vram_helper.c

+2 −5
Original line number Diff line number Diff line
@@ -147,15 +147,12 @@ static void drm_gem_vram_placement(struct drm_gem_vram_object *gbo, 


	if (pl_flag & DRM_GEM_VRAM_PL_FLAG_VRAM) {

		gbo->placements[c].mem_type = TTM_PL_VRAM;

		gbo->placements[c++].flags = TTM_PL_FLAG_WC |

					     TTM_PL_FLAG_UNCACHED |

					     invariant_flags;

		gbo->placements[c++].flags = invariant_flags;

	}



	if (pl_flag & DRM_GEM_VRAM_PL_FLAG_SYSTEM || !c) {

		gbo->placements[c].mem_type = TTM_PL_SYSTEM;

		gbo->placements[c++].flags = TTM_PL_MASK_CACHING |

					     invariant_flags;

		gbo->placements[c++].flags = invariant_flags;

	}



	gbo->placement.num_placement = c;

drivers/gpu/drm/nouveau/nouveau_bo.c

+9 −27
Original line number Diff line number Diff line
@@ -343,37 +343,23 @@ nouveau_bo_new(struct nouveau_cli *cli, u64 size, int align, 
}



static void

set_placement_list(struct nouveau_drm *drm, struct ttm_place *pl, unsigned *n,

		   uint32_t domain, uint32_t flags)

set_placement_list(struct ttm_place *pl, unsigned *n, uint32_t domain)

{

	*n = 0;



	if (domain & NOUVEAU_GEM_DOMAIN_VRAM) {

		struct nvif_mmu *mmu = &drm->client.mmu;

		const u8 type = mmu->type[drm->ttm.type_vram].type;



		pl[*n].mem_type = TTM_PL_VRAM;

		pl[*n].flags = flags & ~TTM_PL_FLAG_CACHED;



		/* Some BARs do not support being ioremapped WC */

		if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_TESLA &&

		    type & NVIF_MEM_UNCACHED)

			pl[*n].flags &= ~TTM_PL_FLAG_WC;



		pl[*n].flags = 0;

		(*n)++;

	}

	if (domain & NOUVEAU_GEM_DOMAIN_GART) {

		pl[*n].mem_type = TTM_PL_TT;

		pl[*n].flags = flags;



		if (drm->agp.bridge)

			pl[*n].flags &= ~TTM_PL_FLAG_CACHED;



		pl[*n].flags = 0;

		(*n)++;

	}

	if (domain & NOUVEAU_GEM_DOMAIN_CPU) {

		pl[*n].mem_type = TTM_PL_SYSTEM;

		pl[(*n)++].flags = flags;

		pl[(*n)++].flags = 0;

	}

}
@@ -415,18 +401,14 @@ void 
nouveau_bo_placement_set(struct nouveau_bo *nvbo, uint32_t domain,

			 uint32_t busy)

{

	struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);

	struct ttm_placement *pl = &nvbo->placement;

	uint32_t flags = nvbo->force_coherent ? TTM_PL_FLAG_UNCACHED :

						TTM_PL_MASK_CACHING;



	pl->placement = nvbo->placements;

	set_placement_list(drm, nvbo->placements, &pl->num_placement,

			   domain, flags);

	set_placement_list(nvbo->placements, &pl->num_placement, domain);



	pl->busy_placement = nvbo->busy_placements;

	set_placement_list(drm, nvbo->busy_placements, &pl->num_busy_placement,

			   domain | busy, flags);

	set_placement_list(nvbo->busy_placements, &pl->num_busy_placement,

			   domain | busy);



	set_placement_range(nvbo, domain);

}
@@ -888,7 +870,7 @@ nouveau_bo_move_flipd(struct ttm_buffer_object *bo, bool evict, 
		.fpfn = 0,

		.lpfn = 0,

		.mem_type = TTM_PL_TT,

		.flags = TTM_PL_MASK_CACHING

		.flags = 0

	};

	struct ttm_placement placement;

	struct ttm_resource tmp_reg;
@@ -930,7 +912,7 @@ nouveau_bo_move_flips(struct ttm_buffer_object *bo, bool evict, 
		.fpfn = 0,

		.lpfn = 0,

		.mem_type = TTM_PL_TT,

		.flags = TTM_PL_MASK_CACHING

		.flags = 0

	};

	struct ttm_placement placement;

	struct ttm_resource tmp_reg;

drivers/gpu/drm/qxl/qxl_object.c

+5 −5
Original line number Diff line number Diff line
@@ -64,21 +64,21 @@ void qxl_ttm_placement_from_domain(struct qxl_bo *qbo, u32 domain) 
	qbo->placement.busy_placement = qbo->placements;

	if (domain == QXL_GEM_DOMAIN_VRAM) {

		qbo->placements[c].mem_type = TTM_PL_VRAM;

		qbo->placements[c++].flags = TTM_PL_FLAG_CACHED | pflag;

		qbo->placements[c++].flags = pflag;

	}

	if (domain == QXL_GEM_DOMAIN_SURFACE) {

		qbo->placements[c].mem_type = TTM_PL_PRIV;

		qbo->placements[c++].flags = TTM_PL_FLAG_CACHED | pflag;

		qbo->placements[c++].flags = pflag;

		qbo->placements[c].mem_type = TTM_PL_VRAM;

		qbo->placements[c++].flags = TTM_PL_FLAG_CACHED | pflag;

		qbo->placements[c++].flags = pflag;

	}

	if (domain == QXL_GEM_DOMAIN_CPU) {

		qbo->placements[c].mem_type = TTM_PL_SYSTEM;

		qbo->placements[c++].flags = TTM_PL_MASK_CACHING | pflag;

		qbo->placements[c++].flags = pflag;

	}

	if (!c) {

		qbo->placements[c].mem_type = TTM_PL_SYSTEM;

		qbo->placements[c++].flags = TTM_PL_MASK_CACHING;

		qbo->placements[c++].flags = 0;

	}

	qbo->placement.num_placement = c;

	qbo->placement.num_busy_placement = c;

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