Commit ce599b1a authored by David S. Miller's avatar David S. Miller
Browse files

Merge branch '1GbE' of git://git.kernel.org/pub/scm/linux/kernel/git/jkirsher/next-queue 



Jeff Kirsher says:

====================
1GbE Intel Wired LAN Driver Updates 2019-07-24

This series contains updates to igc and e1000e client drivers only.

Sasha provides a couple of cleanups to remove code that is not needed
and reduce structure sizes.  Updated the MAC reset flow to use the
device reset flow instead of a port reset flow.  Added addition device
id's that will be supported.

Kai-Heng Feng provides a workaround for a possible stalled packet issue
in our ICH devices due to a clock recovery from the PCH being too slow.

v2: removed the last patch in the series that supposedly fixed a MAC/PHY
    de-sync potential issue while waiting for additional information from
    hardware engineers.
====================

Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents d601be97 e5e9a2ec

drivers/net/ethernet/intel/e1000e/ich8lan.c

+10 −0
Original line number Diff line number Diff line
@@ -1429,6 +1429,16 @@ static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw) 
			else

				phy_reg |= 0xFA;

			e1e_wphy_locked(hw, I217_PLL_CLOCK_GATE_REG, phy_reg);



			if (speed == SPEED_1000) {

				hw->phy.ops.read_reg_locked(hw, HV_PM_CTRL,

							    &phy_reg);



				phy_reg |= HV_PM_CTRL_K1_CLK_REQ;



				hw->phy.ops.write_reg_locked(hw, HV_PM_CTRL,

							     phy_reg);

			}

		}

		hw->phy.ops.release(hw);

drivers/net/ethernet/intel/e1000e/ich8lan.h

+1 −1
Original line number Diff line number Diff line
@@ -210,7 +210,7 @@ 


/* PHY Power Management Control */

#define HV_PM_CTRL		PHY_REG(770, 17)

#define HV_PM_CTRL_PLL_STOP_IN_K1_GIGA	0x100

#define HV_PM_CTRL_K1_CLK_REQ		0x200

#define HV_PM_CTRL_K1_ENABLE		0x4000



#define I217_PLL_CLOCK_GATE_REG	PHY_REG(772, 28)

drivers/net/ethernet/intel/igc/igc_base.c

+4 −1
Original line number Diff line number Diff line
@@ -40,7 +40,7 @@ static s32 igc_reset_hw_base(struct igc_hw *hw) 
	ctrl = rd32(IGC_CTRL);



	hw_dbg("Issuing a global reset to MAC\n");

	wr32(IGC_CTRL, ctrl | IGC_CTRL_RST);

	wr32(IGC_CTRL, ctrl | IGC_CTRL_DEV_RST);



	ret_val = igc_get_auto_rd_done(hw);

	if (ret_val) {
@@ -209,6 +209,9 @@ static s32 igc_get_invariants_base(struct igc_hw *hw) 
	switch (hw->device_id) {

	case IGC_DEV_ID_I225_LM:

	case IGC_DEV_ID_I225_V:

	case IGC_DEV_ID_I225_I:

	case IGC_DEV_ID_I220_V:

	case IGC_DEV_ID_I225_K:

		mac->type = igc_i225;

		break;

	default:

drivers/net/ethernet/intel/igc/igc_defines.h

+1 −1
Original line number Diff line number Diff line
@@ -54,7 +54,7 @@ 
#define IGC_ERR_SWFW_SYNC		13



/* Device Control */

#define IGC_CTRL_RST		0x04000000  /* Global reset */

#define IGC_CTRL_DEV_RST	0x20000000  /* Device reset */



#define IGC_CTRL_PHY_RST	0x80000000  /* PHY Reset */

#define IGC_CTRL_SLU		0x00000040  /* Set link up (Force Link) */

drivers/net/ethernet/intel/igc/igc_hw.h

+3 −11
Original line number Diff line number Diff line
@@ -18,6 +18,9 @@ 


#define IGC_DEV_ID_I225_LM			0x15F2

#define IGC_DEV_ID_I225_V			0x15F3

#define IGC_DEV_ID_I225_I			0x15F8

#define IGC_DEV_ID_I220_V			0x15F7

#define IGC_DEV_ID_I225_K			0x3100



#define IGC_FUNC_0				0
@@ -151,16 +154,10 @@ struct igc_phy_info { 


	u16 autoneg_advertised;

	u16 autoneg_mask;

	u16 cable_length;

	u16 max_cable_length;

	u16 min_cable_length;

	u16 pair_length[4];



	u8 mdix;



	bool disable_polarity_correction;

	bool is_mdix;

	bool polarity_correction;

	bool reset_disable;

	bool speed_downgraded;

	bool autoneg_wait_to_complete;
@@ -190,12 +187,7 @@ struct igc_fc_info { 
};



struct igc_dev_spec_base {

	bool global_device_reset;

	bool eee_disable;

	bool clear_semaphore_once;

	bool module_plugged;

	u8 media_port;

	bool mas_capable;

};



struct igc_hw {

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