Commit ce436254 authored by Stephen Warren's avatar Stephen Warren Committed by Linus Walleij
Browse files

pinctrl: tegra: dynamically calculate function list of groups 



The per-SoC data structures for Tegra pinctrl stored some information
in a redundant way. Specifically, the list of groups that each function
could be muxed onto was stored once explicitly, and also as part of the
definition of each group. Eliminate this redundancy, and calculate each
function's list of valid groups at pinctrl probe time. This removes
thousands of lines of code from the pinctrl driver and ~16K from the
vmlinux binary size, and adds only about 500uS to the boot process (on
Tegra30; newer SoCs will likely be faster still).

Signed-off-by: default avatarStephen Warren <swarren@nvidia.com>
Signed-off-by: default avatarLinus Walleij <linus.walleij@linaro.org>
parent edfab368

drivers/pinctrl/pinctrl-tegra.c

+38 −0
Original line number Diff line number Diff line
@@ -39,6 +39,7 @@ struct tegra_pmx { 
	struct pinctrl_dev *pctl;



	const struct tegra_pinctrl_soc_data *soc;

	const char **group_pins;



	int nbanks;

	void __iomem **regs;
@@ -620,6 +621,8 @@ int tegra_pinctrl_probe(struct platform_device *pdev, 
	struct tegra_pmx *pmx;

	struct resource *res;

	int i;

	const char **group_pins;

	int fn, gn, gfn;



	pmx = devm_kzalloc(&pdev->dev, sizeof(*pmx), GFP_KERNEL);

	if (!pmx) {
@@ -629,6 +632,41 @@ int tegra_pinctrl_probe(struct platform_device *pdev, 
	pmx->dev = &pdev->dev;

	pmx->soc = soc_data;



	/*

	 * Each mux group will appear in 4 functions' list of groups.

	 * This over-allocates slightly, since not all groups are mux groups.

	 */

	pmx->group_pins = devm_kzalloc(&pdev->dev,

		soc_data->ngroups * 4 * sizeof(*pmx->group_pins),

		GFP_KERNEL);

	if (!pmx->group_pins)

		return -ENOMEM;



	group_pins = pmx->group_pins;

	for (fn = 0; fn < soc_data->nfunctions; fn++) {

		struct tegra_function *func = &soc_data->functions[fn];



		func->groups = group_pins;



		for (gn = 0; gn < soc_data->ngroups; gn++) {

			const struct tegra_pingroup *g = &soc_data->groups[gn];



			if (g->mux_reg == -1)

				continue;



			for (gfn = 0; gfn < 4; gfn++)

				if (g->funcs[gfn] == fn)

					break;

			if (gfn == 4)

				continue;



			BUG_ON(group_pins - pmx->group_pins >=

				soc_data->ngroups * 4);

			*group_pins++ = g->name;

			func->ngroups++;

		}

	}



	tegra_pinctrl_gpio_range.npins = pmx->soc->ngpios;

	tegra_pinctrl_desc.name = dev_name(&pdev->dev);

	tegra_pinctrl_desc.pins = pmx->soc->pins;

drivers/pinctrl/pinctrl-tegra.h

+2 −2
Original line number Diff line number Diff line
@@ -72,7 +72,7 @@ enum tegra_pinconf_tristate { 
 */

struct tegra_function {

	const char *name;

	const char * const *groups;

	const char **groups;

	unsigned ngroups;

};
@@ -193,7 +193,7 @@ struct tegra_pinctrl_soc_data { 
	unsigned ngpios;

	const struct pinctrl_pin_desc *pins;

	unsigned npins;

	const struct tegra_function *functions;

	struct tegra_function *functions;

	unsigned nfunctions;

	const struct tegra_pingroup *groups;

	unsigned ngroups;

drivers/pinctrl/pinctrl-tegra114.c

+1 −930
Original line number Diff line number Diff line
@@ -1420,941 +1420,12 @@ enum tegra_mux { 
	TEGRA_MUX_VI_ALT3,

};



static const char * const blink_groups[] = {

	"clk_32k_out_pa0",

};



static const char * const cec_groups[] = {

	"hdmi_cec_pee3",

};



static const char * const cldvfs_groups[] = {

	"gmi_ad9_ph1",

	"gmi_ad10_ph2",

	"kb_row7_pr7",

	"kb_row8_ps0",

	"dvfs_pwm_px0",

	"dvfs_clk_px2",

};



static const char * const clk12_groups[] = {

	"sdmmc1_wp_n_pv3",

	"sdmmc1_clk_pz0",

};



static const char * const cpu_groups[] = {

	"cpu_pwr_req",

};



static const char * const dap_groups[] = {

	"clk1_req_pee2",

	"clk2_req_pcc5",

};



static const char * const dap1_groups[] = {

	"clk1_req_pee2",

};



static const char * const dap2_groups[] = {

	"clk1_out_pw4",

	"gpio_x4_aud_px4",

};



static const char * const dev3_groups[] = {

	"clk3_req_pee1",

};



static const char * const displaya_groups[] = {

	"dap3_fs_pp0",

	"dap3_din_pp1",

	"dap3_dout_pp2",

	"dap3_sclk_pp3",

	"uart3_rts_n_pc0",

	"pu3",

	"pu4",

	"pu5",

	"pbb3",

	"pbb4",

	"pbb5",

	"pbb6",

	"kb_row3_pr3",

	"kb_row4_pr4",

	"kb_row5_pr5",

	"kb_row6_pr6",

	"kb_col3_pq3",

	"sdmmc3_dat2_pb5",

};



static const char * const displaya_alt_groups[] = {

	"kb_row6_pr6",

};



static const char * const displayb_groups[] = {

	"dap3_fs_pp0",

	"dap3_din_pp1",

	"dap3_dout_pp2",

	"dap3_sclk_pp3",

	"pu3",

	"pu4",

	"pu5",

	"pu6",

	"pbb3",

	"pbb4",

	"pbb5",

	"pbb6",

	"kb_row3_pr3",

	"kb_row4_pr4",

	"kb_row5_pr5",

	"kb_row6_pr6",

	"sdmmc3_dat3_pb4",

};



static const char * const dtv_groups[] = {

	"uart3_cts_n_pa1",

	"uart3_rts_n_pc0",

	"dap4_fs_pp4",

	"dap4_dout_pp6",

	"gmi_wait_pi7",

	"gmi_ad8_ph0",

	"gmi_ad14_ph6",

	"gmi_ad15_ph7",

};



static const char * const emc_dll_groups[] = {

	"kb_col0_pq0",

	"kb_col1_pq1",

};



static const char * const extperiph1_groups[] = {

	"clk1_out_pw4",

};



static const char * const extperiph2_groups[] = {

	"clk2_out_pw5",

};



static const char * const extperiph3_groups[] = {

	"clk3_out_pee0",

};



static const char * const gmi_groups[] = {

	"gmi_wp_n_pc7",



	"gmi_ad0_pg0",

	"gmi_ad1_pg1",

	"gmi_ad2_pg2",

	"gmi_ad3_pg3",

	"gmi_ad4_pg4",

	"gmi_ad5_pg5",

	"gmi_ad6_pg6",

	"gmi_ad7_pg7",

	"gmi_ad8_ph0",

	"gmi_ad9_ph1",

	"gmi_ad10_ph2",

	"gmi_ad11_ph3",

	"gmi_ad12_ph4",

	"gmi_ad13_ph5",

	"gmi_ad14_ph6",

	"gmi_ad15_ph7",

	"gmi_wr_n_pi0",

	"gmi_oe_n_pi1",

	"gmi_cs6_n_pi3",

	"gmi_rst_n_pi4",

	"gmi_iordy_pi5",

	"gmi_cs7_n_pi6",

	"gmi_wait_pi7",

	"gmi_cs0_n_pj0",

	"gmi_cs1_n_pj2",

	"gmi_dqs_p_pj3",

	"gmi_adv_n_pk0",

	"gmi_clk_pk1",

	"gmi_cs4_n_pk2",

	"gmi_cs2_n_pk3",

	"gmi_cs3_n_pk4",

	"gmi_a16_pj7",

	"gmi_a17_pb0",

	"gmi_a18_pb1",

	"gmi_a19_pk7",

	"gen2_i2c_scl_pt5",

	"gen2_i2c_sda_pt6",

	"sdmmc4_dat0_paa0",

	"sdmmc4_dat1_paa1",

	"sdmmc4_dat2_paa2",

	"sdmmc4_dat3_paa3",

	"sdmmc4_dat4_paa4",

	"sdmmc4_dat5_paa5",

	"sdmmc4_dat6_paa6",

	"sdmmc4_dat7_paa7",

	"sdmmc4_clk_pcc4",

	"sdmmc4_cmd_pt7",

	"dap1_fs_pn0",

	"dap1_din_pn1",

	"dap1_dout_pn2",

	"dap1_sclk_pn3",

};



static const char * const gmi_alt_groups[] = {

	"gmi_wp_n_pc7",

	"gmi_cs3_n_pk4",

	"gmi_a16_pj7",

};



static const char * const hda_groups[] = {

	"dap1_fs_pn0",

	"dap1_din_pn1",

	"dap1_dout_pn2",

	"dap1_sclk_pn3",

	"dap2_fs_pa2",

	"dap2_sclk_pa3",

	"dap2_din_pa4",

	"dap2_dout_pa5",

};



static const char * const hsi_groups[] = {

	"ulpi_data0_po1",

	"ulpi_data1_po2",

	"ulpi_data2_po3",

	"ulpi_data3_po4",

	"ulpi_data4_po5",

	"ulpi_data5_po6",

	"ulpi_data6_po7",

	"ulpi_data7_po0",

};



static const char * const i2c1_groups[] = {

	"gen1_i2c_scl_pc4",

	"gen1_i2c_sda_pc5",

	"gpio_w2_aud_pw2",

	"gpio_w3_aud_pw3",

};



static const char * const i2c2_groups[] = {

	"gen2_i2c_scl_pt5",

	"gen2_i2c_sda_pt6",

};



static const char * const i2c3_groups[] = {

	"cam_i2c_scl_pbb1",

	"cam_i2c_sda_pbb2",

};



static const char * const i2c4_groups[] = {

	"ddc_scl_pv4",

	"ddc_sda_pv5",

};



static const char * const i2cpwr_groups[] = {

	"pwr_i2c_scl_pz6",

	"pwr_i2c_sda_pz7",

};



static const char * const i2s0_groups[] = {

	"dap1_fs_pn0",

	"dap1_din_pn1",

	"dap1_dout_pn2",

	"dap1_sclk_pn3",

};



static const char * const i2s1_groups[] = {

	"dap2_fs_pa2",

	"dap2_sclk_pa3",

	"dap2_din_pa4",

	"dap2_dout_pa5",

};



static const char * const i2s2_groups[] = {

	"dap3_fs_pp0",

	"dap3_din_pp1",

	"dap3_dout_pp2",

	"dap3_sclk_pp3",

};



static const char * const i2s3_groups[] = {

	"dap4_fs_pp4",

	"dap4_din_pp5",

	"dap4_dout_pp6",

	"dap4_sclk_pp7",

};



static const char * const i2s4_groups[] = {

	"pcc1",

	"pbb0",

	"pbb7",

	"pcc2",

};



static const char * const irda_groups[] = {

	"uart2_rxd_pc3",

	"uart2_txd_pc2",

};



static const char * const kbc_groups[] = {

	"kb_row0_pr0",

	"kb_row1_pr1",

	"kb_row2_pr2",

	"kb_row3_pr3",

	"kb_row4_pr4",

	"kb_row5_pr5",

	"kb_row6_pr6",

	"kb_row7_pr7",

	"kb_row8_ps0",

	"kb_row9_ps1",

	"kb_row10_ps2",

	"kb_col0_pq0",

	"kb_col1_pq1",

	"kb_col2_pq2",

	"kb_col3_pq3",

	"kb_col4_pq4",

	"kb_col5_pq5",

	"kb_col6_pq6",

	"kb_col7_pq7",

};



static const char * const nand_groups[] = {

	"gmi_wp_n_pc7",

	"gmi_wait_pi7",

	"gmi_adv_n_pk0",

	"gmi_clk_pk1",

	"gmi_cs0_n_pj0",

	"gmi_cs1_n_pj2",

	"gmi_cs2_n_pk3",

	"gmi_cs3_n_pk4",

	"gmi_cs4_n_pk2",

	"gmi_cs6_n_pi3",

	"gmi_cs7_n_pi6",

	"gmi_ad0_pg0",

	"gmi_ad1_pg1",

	"gmi_ad2_pg2",

	"gmi_ad3_pg3",

	"gmi_ad4_pg4",

	"gmi_ad5_pg5",

	"gmi_ad6_pg6",

	"gmi_ad7_pg7",

	"gmi_ad8_ph0",

	"gmi_ad9_ph1",

	"gmi_ad10_ph2",

	"gmi_ad11_ph3",

	"gmi_ad12_ph4",

	"gmi_ad13_ph5",

	"gmi_ad14_ph6",

	"gmi_ad15_ph7",

	"gmi_wr_n_pi0",

	"gmi_oe_n_pi1",

	"gmi_dqs_p_pj3",

	"gmi_rst_n_pi4",

};



static const char * const nand_alt_groups[] = {

	"gmi_cs6_n_pi3",

	"gmi_cs7_n_pi6",

	"gmi_rst_n_pi4",

};



static const char * const owr_groups[] = {

	"pu0",

	"kb_col4_pq4",

	"owr",

	"sdmmc3_cd_n_pv2",

};



static const char * const pmi_groups[] = {

	"pwr_int_n",

};



static const char * const pwm0_groups[] = {

	"sdmmc1_dat2_py5",

	"uart3_rts_n_pc0",

	"pu3",

	"gmi_ad8_ph0",

	"sdmmc3_dat3_pb4",

};



static const char * const pwm1_groups[] = {

	"sdmmc1_dat1_py6",

	"pu4",

	"gmi_ad9_ph1",

	"sdmmc3_dat2_pb5",

};



static const char * const pwm2_groups[] = {

	"pu5",

	"gmi_ad10_ph2",

	"kb_col3_pq3",

	"sdmmc3_dat1_pb6",

};



static const char * const pwm3_groups[] = {

	"pu6",

	"gmi_ad11_ph3",

	"sdmmc3_cmd_pa7",

};



static const char * const pwron_groups[] = {

	"core_pwr_req",

};



static const char * const reset_out_n_groups[] = {

	"reset_out_n",

};



static const char * const rsvd1_groups[] = {

	"pv1",

	"hdmi_int_pn7",

	"pu1",

	"pu2",

	"gmi_wp_n_pc7",

	"gmi_adv_n_pk0",

	"gmi_cs0_n_pj0",

	"gmi_cs1_n_pj2",

	"gmi_ad0_pg0",

	"gmi_ad1_pg1",

	"gmi_ad2_pg2",

	"gmi_ad3_pg3",

	"gmi_ad4_pg4",

	"gmi_ad5_pg5",

	"gmi_ad6_pg6",

	"gmi_ad7_pg7",

	"gmi_wr_n_pi0",

	"gmi_oe_n_pi1",

	"gpio_x4_aud_px4",

	"gpio_x5_aud_px5",

	"gpio_x7_aud_px7",



	"reset_out_n",

};



static const char * const rsvd2_groups[] = {

	"pv0",

	"pv1",

	"sdmmc1_dat0_py7",

	"clk2_out_pw5",

	"clk2_req_pcc5",

	"hdmi_int_pn7",

	"ddc_scl_pv4",

	"ddc_sda_pv5",

	"uart3_txd_pw6",

	"uart3_rxd_pw7",

	"gen1_i2c_scl_pc4",

	"gen1_i2c_sda_pc5",

	"dap4_fs_pp4",

	"dap4_din_pp5",

	"dap4_dout_pp6",

	"dap4_sclk_pp7",

	"clk3_out_pee0",

	"clk3_req_pee1",

	"gmi_iordy_pi5",

	"gmi_a17_pb0",

	"gmi_a18_pb1",

	"gen2_i2c_scl_pt5",

	"gen2_i2c_sda_pt6",

	"sdmmc4_clk_pcc4",

	"sdmmc4_cmd_pt7",

	"sdmmc4_dat7_paa7",

	"pcc1",

	"pbb7",

	"pcc2",

	"pwr_i2c_scl_pz6",

	"pwr_i2c_sda_pz7",

	"kb_row0_pr0",

	"kb_row1_pr1",

	"kb_row2_pr2",

	"kb_row7_pr7",

	"kb_row8_ps0",

	"kb_row9_ps1",

	"kb_row10_ps2",

	"kb_col1_pq1",

	"kb_col2_pq2",

	"kb_col5_pq5",

	"kb_col6_pq6",

	"kb_col7_pq7",

	"sys_clk_req_pz5",

	"core_pwr_req",

	"cpu_pwr_req",

	"pwr_int_n",

	"owr",

	"spdif_out_pk5",

	"gpio_x1_aud_px1",

	"sdmmc3_clk_pa6",

	"sdmmc3_dat0_pb7",

	"gpio_w2_aud_pw2",

	"usb_vbus_en0_pn4",

	"usb_vbus_en1_pn5",

	"sdmmc3_clk_lb_out_pee4",

	"sdmmc3_clk_lb_in_pee5",

	"reset_out_n",

};



static const char * const rsvd3_groups[] = {

	"pv0",

	"pv1",

	"sdmmc1_clk_pz0",

	"clk2_out_pw5",

	"clk2_req_pcc5",

	"hdmi_int_pn7",

	"ddc_scl_pv4",

	"ddc_sda_pv5",

	"uart2_rts_n_pj6",

	"uart2_cts_n_pj5",

	"uart3_txd_pw6",

	"uart3_rxd_pw7",

	"pu0",

	"pu1",

	"pu2",

	"gen1_i2c_scl_pc4",

	"gen1_i2c_sda_pc5",

	"dap4_din_pp5",

	"dap4_sclk_pp7",

	"clk3_out_pee0",

	"clk3_req_pee1",

	"pcc1",

	"cam_i2c_scl_pbb1",

	"cam_i2c_sda_pbb2",

	"pbb7",

	"pcc2",

	"pwr_i2c_scl_pz6",

	"pwr_i2c_sda_pz7",

	"kb_row0_pr0",

	"kb_row1_pr1",

	"kb_row2_pr2",

	"kb_row3_pr3",

	"kb_row9_ps1",

	"kb_row10_ps2",

	"clk_32k_out_pa0",

	"sys_clk_req_pz5",

	"core_pwr_req",

	"cpu_pwr_req",

	"pwr_int_n",

	"owr",

	"clk1_req_pee2",

	"clk1_out_pw4",

	"spdif_out_pk5",

	"spdif_in_pk6",

	"dap2_fs_pa2",

	"dap2_sclk_pa3",

	"dap2_din_pa4",

	"dap2_dout_pa5",

	"dvfs_pwm_px0",

	"gpio_x1_aud_px1",

	"gpio_x3_aud_px3",

	"dvfs_clk_px2",

	"sdmmc3_clk_pa6",

	"sdmmc3_dat0_pb7",

	"hdmi_cec_pee3",

	"sdmmc3_cd_n_pv2",

	"usb_vbus_en0_pn4",

	"usb_vbus_en1_pn5",

	"sdmmc3_clk_lb_out_pee4",

	"sdmmc3_clk_lb_in_pee5",

	"reset_out_n",

};



static const char * const rsvd4_groups[] = {

	"pv0",

	"pv1",

	"sdmmc1_clk_pz0",

	"clk2_out_pw5",

	"clk2_req_pcc5",

	"hdmi_int_pn7",

	"ddc_scl_pv4",

	"ddc_sda_pv5",

	"pu0",

	"pu1",

	"pu2",

	"gen1_i2c_scl_pc4",

	"gen1_i2c_sda_pc5",

	"dap4_fs_pp4",

	"dap4_din_pp5",

	"dap4_dout_pp6",

	"dap4_sclk_pp7",

	"clk3_out_pee0",

	"clk3_req_pee1",

	"gmi_ad0_pg0",

	"gmi_ad1_pg1",

	"gmi_ad2_pg2",

	"gmi_ad3_pg3",

	"gmi_ad4_pg4",

	"gmi_ad12_ph4",

	"gmi_ad13_ph5",

	"gmi_rst_n_pi4",

	"gen2_i2c_scl_pt5",

	"gen2_i2c_sda_pt6",

	"sdmmc4_clk_pcc4",

	"sdmmc4_cmd_pt7",

	"sdmmc4_dat0_paa0",

	"sdmmc4_dat1_paa1",

	"sdmmc4_dat2_paa2",

	"sdmmc4_dat3_paa3",

	"sdmmc4_dat4_paa4",

	"sdmmc4_dat5_paa5",

	"sdmmc4_dat6_paa6",

	"sdmmc4_dat7_paa7",

	"cam_mclk_pcc0",

	"pcc1",

	"cam_i2c_scl_pbb1",

	"cam_i2c_sda_pbb2",

	"pbb3",

	"pbb4",

	"pbb5",

	"pbb6",

	"pbb7",

	"pcc2",

	"pwr_i2c_scl_pz6",

	"pwr_i2c_sda_pz7",

	"kb_row0_pr0",

	"kb_row1_pr1",

	"kb_row2_pr2",

	"kb_col2_pq2",

	"kb_col5_pq5",

	"kb_col6_pq6",

	"kb_col7_pq7",

	"clk_32k_out_pa0",

	"sys_clk_req_pz5",

	"core_pwr_req",

	"cpu_pwr_req",

	"pwr_int_n",

	"owr",

	"dap1_fs_pn0",

	"dap1_din_pn1",

	"dap1_dout_pn2",

	"dap1_sclk_pn3",

	"clk1_req_pee2",

	"clk1_out_pw4",

	"spdif_in_pk6",

	"spdif_out_pk5",

	"dap2_fs_pa2",

	"dap2_sclk_pa3",

	"dap2_din_pa4",

	"dap2_dout_pa5",

	"dvfs_pwm_px0",

	"gpio_x1_aud_px1",

	"gpio_x3_aud_px3",

	"dvfs_clk_px2",

	"gpio_x5_aud_px5",

	"gpio_x6_aud_px6",

	"gpio_x7_aud_px7",

	"sdmmc3_cd_n_pv2",

	"usb_vbus_en0_pn4",

	"usb_vbus_en1_pn5",

	"sdmmc3_clk_lb_in_pee5",

	"sdmmc3_clk_lb_out_pee4",

};



static const char * const sdmmc1_groups[] = {



	"sdmmc1_clk_pz0",

	"sdmmc1_cmd_pz1",

	"sdmmc1_dat3_py4",

	"sdmmc1_dat2_py5",

	"sdmmc1_dat1_py6",

	"sdmmc1_dat0_py7",

	"uart3_cts_n_pa1",

	"kb_col5_pq5",

	"sdmmc1_wp_n_pv3",

};



static const char * const sdmmc2_groups[] = {

	"gmi_iordy_pi5",

	"gmi_clk_pk1",

	"gmi_cs2_n_pk3",

	"gmi_cs3_n_pk4",

	"gmi_cs7_n_pi6",

	"gmi_ad12_ph4",

	"gmi_ad13_ph5",

	"gmi_ad14_ph6",

	"gmi_ad15_ph7",

	"gmi_dqs_p_pj3",

};



static const char * const sdmmc3_groups[] = {

	"kb_col4_pq4",

	"sdmmc3_clk_pa6",

	"sdmmc3_cmd_pa7",

	"sdmmc3_dat0_pb7",

	"sdmmc3_dat1_pb6",

	"sdmmc3_dat2_pb5",

	"sdmmc3_dat3_pb4",

	"hdmi_cec_pee3",

	"sdmmc3_cd_n_pv2",

	"sdmmc3_clk_lb_in_pee5",

	"sdmmc3_clk_lb_out_pee4",

};



static const char * const sdmmc4_groups[] = {

	"sdmmc4_clk_pcc4",

	"sdmmc4_cmd_pt7",

	"sdmmc4_dat0_paa0",

	"sdmmc4_dat1_paa1",

	"sdmmc4_dat2_paa2",

	"sdmmc4_dat3_paa3",

	"sdmmc4_dat4_paa4",

	"sdmmc4_dat5_paa5",

	"sdmmc4_dat6_paa6",

	"sdmmc4_dat7_paa7",

};



static const char * const soc_groups[] = {

	"gmi_cs1_n_pj2",

	"gmi_oe_n_pi1",

	"clk_32k_out_pa0",

	"hdmi_cec_pee3",

};



static const char * const spdif_groups[] = {

	"sdmmc1_cmd_pz1",

	"sdmmc1_dat3_py4",

	"uart2_rxd_pc3",

	"uart2_txd_pc2",

	"spdif_in_pk6",

	"spdif_out_pk5",

};



static const char * const spi1_groups[] = {

	"ulpi_clk_py0",

	"ulpi_dir_py1",

	"ulpi_nxt_py2",

	"ulpi_stp_py3",

	"gpio_x3_aud_px3",

	"gpio_x4_aud_px4",

	"gpio_x5_aud_px5",

	"gpio_x6_aud_px6",

	"gpio_x7_aud_px7",

	"gpio_w3_aud_pw3",

};



static const char * const spi2_groups[] = {

	"ulpi_data4_po5",

	"ulpi_data5_po6",

	"ulpi_data6_po7",

	"ulpi_data7_po0",

	"kb_row4_pr4",

	"kb_row5_pr5",

	"kb_col0_pq0",

	"kb_col1_pq1",

	"kb_col2_pq2",

	"kb_col6_pq6",

	"kb_col7_pq7",

	"gpio_x4_aud_px4",

	"gpio_x5_aud_px5",

	"gpio_x6_aud_px6",

	"gpio_x7_aud_px7",

	"gpio_w2_aud_pw2",

	"gpio_w3_aud_pw3",

};



static const char * const spi3_groups[] = {

	"ulpi_data0_po1",

	"ulpi_data1_po2",

	"ulpi_data2_po3",

	"ulpi_data3_po4",

	"sdmmc4_dat0_paa0",

	"sdmmc4_dat1_paa1",

	"sdmmc4_dat2_paa2",

	"sdmmc4_dat3_paa3",

	"sdmmc4_dat4_paa4",

	"sdmmc4_dat5_paa5",

	"sdmmc4_dat6_paa6",

	"sdmmc3_clk_pa6",

	"sdmmc3_cmd_pa7",

	"sdmmc3_dat0_pb7",

	"sdmmc3_dat1_pb6",

	"sdmmc3_dat2_pb5",

	"sdmmc3_dat3_pb4",

};



static const char * const spi4_groups[] = {

	"sdmmc1_cmd_pz1",

	"sdmmc1_dat3_py4",

	"sdmmc1_dat2_py5",

	"sdmmc1_dat1_py6",

	"sdmmc1_dat0_py7",

	"uart2_rxd_pc3",

	"uart2_txd_pc2",

	"uart2_rts_n_pj6",

	"uart2_cts_n_pj5",

	"uart3_txd_pw6",

	"uart3_rxd_pw7",

	"uart3_cts_n_pa1",

	"gmi_wait_pi7",

	"gmi_cs6_n_pi3",

	"gmi_ad5_pg5",

	"gmi_ad6_pg6",

	"gmi_ad7_pg7",

	"gmi_a19_pk7",

	"gmi_wr_n_pi0",

	"sdmmc1_wp_n_pv3",

};



static const char * const spi5_groups[] = {

	"ulpi_clk_py0",

	"ulpi_dir_py1",

	"ulpi_nxt_py2",

	"ulpi_stp_py3",

	"dap3_fs_pp0",

	"dap3_din_pp1",

	"dap3_dout_pp2",

	"dap3_sclk_pp3",

};



static const char * const spi6_groups[] = {

	"dvfs_pwm_px0",

	"gpio_x1_aud_px1",

	"gpio_x3_aud_px3",

	"dvfs_clk_px2",

	"gpio_x6_aud_px6",

	"gpio_w2_aud_pw2",

	"gpio_w3_aud_pw3",

};



static const char * const sysclk_groups[] = {

	"sys_clk_req_pz5",

};



static const char * const trace_groups[] = {

	"gmi_iordy_pi5",

	"gmi_adv_n_pk0",

	"gmi_clk_pk1",

	"gmi_cs2_n_pk3",

	"gmi_cs4_n_pk2",

	"gmi_a16_pj7",

	"gmi_a17_pb0",

	"gmi_a18_pb1",

	"gmi_a19_pk7",

	"gmi_dqs_p_pj3",

};



static const char * const uarta_groups[] = {

	"ulpi_data0_po1",

	"ulpi_data1_po2",

	"ulpi_data2_po3",

	"ulpi_data3_po4",

	"ulpi_data4_po5",

	"ulpi_data5_po6",

	"ulpi_data6_po7",

	"ulpi_data7_po0",

	"sdmmc1_cmd_pz1",

	"sdmmc1_dat3_py4",

	"sdmmc1_dat2_py5",

	"sdmmc1_dat1_py6",

	"sdmmc1_dat0_py7",

	"uart2_rxd_pc3",

	"uart2_txd_pc2",

	"uart2_rts_n_pj6",

	"uart2_cts_n_pj5",

	"pu0",

	"pu1",

	"pu2",

	"pu3",

	"pu4",

	"pu5",

	"pu6",

	"kb_row7_pr7",

	"kb_row8_ps0",

	"kb_row9_ps1",

	"kb_row10_ps2",

	"kb_col3_pq3",

	"kb_col4_pq4",

	"sdmmc3_cmd_pa7",

	"sdmmc3_dat1_pb6",

	"sdmmc1_wp_n_pv3",

};



static const char * const uartb_groups[] = {

	"uart2_rts_n_pj6",

	"uart2_cts_n_pj5",

};



static const char * const uartc_groups[] = {

	"uart3_txd_pw6",

	"uart3_rxd_pw7",

	"uart3_cts_n_pa1",

	"uart3_rts_n_pc0",

};



static const char * const uartd_groups[] = {

	"ulpi_clk_py0",

	"ulpi_dir_py1",

	"ulpi_nxt_py2",

	"ulpi_stp_py3",

	"gmi_a16_pj7",

	"gmi_a17_pb0",

	"gmi_a18_pb1",

	"gmi_a19_pk7",

};



static const char * const ulpi_groups[] = {

	"ulpi_data0_po1",

	"ulpi_data1_po2",

	"ulpi_data2_po3",

	"ulpi_data3_po4",

	"ulpi_data4_po5",

	"ulpi_data5_po6",

	"ulpi_data6_po7",

	"ulpi_data7_po0",

	"ulpi_clk_py0",

	"ulpi_dir_py1",

	"ulpi_nxt_py2",

	"ulpi_stp_py3",

};



static const char * const usb_groups[] = {

	"pv0",

	"pu6",

	"gmi_cs0_n_pj0",

	"gmi_cs4_n_pk2",

	"gmi_ad11_ph3",

	"kb_col0_pq0",

	"spdif_in_pk6",

	"usb_vbus_en0_pn4",

	"usb_vbus_en1_pn5",

};



static const char * const vgp1_groups[] = {

	"cam_i2c_scl_pbb1",

};



static const char * const vgp2_groups[] = {

	"cam_i2c_sda_pbb2",

};



static const char * const vgp3_groups[] = {

	"pbb3",

};



static const char * const vgp4_groups[] = {

	"pbb4",

};



static const char * const vgp5_groups[] = {

	"pbb5",

};



static const char * const vgp6_groups[] = {

	"pbb6",

};



static const char * const vi_groups[] = {

	"cam_mclk_pcc0",

	"pbb0",

};



static const char * const vi_alt1_groups[] = {

	"cam_mclk_pcc0",

	"pbb0",

};



static const char * const vi_alt3_groups[] = {

	"cam_mclk_pcc0",

	"pbb0",

};



#define FUNCTION(fname)					\

	{						\

		.name = #fname,				\

		.groups = fname##_groups,		\

		.ngroups = ARRAY_SIZE(fname##_groups),	\

	}



static const struct tegra_function  tegra114_functions[] = {

static struct tegra_function  tegra114_functions[] = {

	FUNCTION(blink),

	FUNCTION(cec),

	FUNCTION(cldvfs),

drivers/pinctrl/pinctrl-tegra124.c

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drivers/pinctrl/pinctrl-tegra20.c

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