Commit ce40141f authored by Daniel Vetter's avatar Daniel Vetter
Browse files

drm/i915: implement WADP0ClockGatingDisable 



Found in Bspec vol4h South Display Engine Registers [CPT, PPT],
section "5.3.1  TRANS_CHICKEN_1—Transcoder Chicken Bits 1"

v2: Make it compile.

Reviewed-by: default avatarPaulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 23670b32

drivers/gpu/drm/i915/i915_reg.h

+4 −0
Original line number Diff line number Diff line
@@ -3824,6 +3824,10 @@ 
#define  TRANS_6BPC             (2<<5)

#define  TRANS_12BPC            (3<<5)



#define _TRANSA_CHICKEN1	 0xf0060

#define _TRANSB_CHICKEN1	 0xf1060

#define TRANS_CHICKEN1(pipe) _PIPE(pipe, _TRANSA_CHICKEN1, _TRANSB_CHICKEN1)

#define  TRANS_CHICKEN1_DP0UNIT_GC_DISABLE	(1<<4)

#define _TRANSA_CHICKEN2	 0xf0064

#define _TRANSB_CHICKEN2	 0xf1064

#define TRANS_CHICKEN2(pipe) _PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2)

drivers/gpu/drm/i915/intel_pm.c

+6 −0
Original line number Diff line number Diff line
@@ -3794,6 +3794,7 @@ static void ibx_init_clock_gating(struct drm_device *dev) 
static void cpt_init_clock_gating(struct drm_device *dev)

{

	struct drm_i915_private *dev_priv = dev->dev_private;

	int pipe;



	/*

	 * On Ibex Peak and Cougar Point, we need to disable clock
@@ -3803,6 +3804,11 @@ static void cpt_init_clock_gating(struct drm_device *dev) 
	I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);

	I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |

		   DPLS_EDP_PPS_FIX_DIS);

	/* WADP0ClockGatingDisable */

	for_each_pipe(pipe) {

		I915_WRITE(TRANS_CHICKEN1(pipe),

			   TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);

	}

}



void intel_init_clock_gating(struct drm_device *dev)

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