Commit ce21f290 authored by Biju Das's avatar Biju Das Committed by Geert Uytterhoeven
Browse files

arm64: dts: renesas: r8a774b1: Add OPPs table for cpu devices 



This patch adds OPPs table for CA57{0,1} cpu devices.

Signed-off-by: default avatarBiju Das <biju.das@bp.renesas.com>
Link: https://lore.kernel.org/r/1569250648-33857-2-git-send-email-biju.das@bp.renesas.com


Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
parent 65005e6a

arch/arm64/boot/dts/renesas/r8a774b1.dtsi

+24 −0
Original line number Diff line number Diff line
@@ -45,6 +45,28 @@ 
		clock-frequency = <0>;

	};



	cluster0_opp: opp_table0 {

		compatible = "operating-points-v2";

		opp-shared;



		opp-500000000 {

			opp-hz = /bits/ 64 <500000000>;

			opp-microvolt = <830000>;

			clock-latency-ns = <300000>;

		};

		opp-1000000000 {

			opp-hz = /bits/ 64 <1000000000>;

			opp-microvolt = <830000>;

			clock-latency-ns = <300000>;

		};

		opp-1500000000 {

			opp-hz = /bits/ 64 <1500000000>;

			opp-microvolt = <830000>;

			clock-latency-ns = <300000>;

			opp-suspend;

		};

	};



	cpus {

		#address-cells = <1>;

		#size-cells = <0>;
@@ -59,6 +81,7 @@ 
			#cooling-cells = <2>;

			dynamic-power-coefficient = <854>;

			clocks = <&cpg CPG_CORE R8A774B1_CLK_Z>;

			operating-points-v2 = <&cluster0_opp>;

		};



		a57_1: cpu@1 {
@@ -69,6 +92,7 @@ 
			next-level-cache = <&L2_CA57>;

			enable-method = "psci";

			clocks = <&cpg CPG_CORE R8A774B1_CLK_Z>;

			operating-points-v2 = <&cluster0_opp>;

		};



		L2_CA57: cache-controller-0 {

CRA Git | Maintained and supported by SUSTech CRA and CCSE