Commit cdb42bec authored by James Smart's avatar James Smart Committed by Martin K. Petersen
Browse files

scsi: lpfc: Replace io_channels for nvme and fcp with general hdw_queues per cpu 



Currently, both nvme and fcp each have their own concept of an io_channel,
which is a combination wq/cq and associated msix.  Different cpus would
share an io_channel.

The driver is now moving to per-cpu wq/cq pairs and msix vectors.  The
driver will still use separate wq/cq pairs per protocol on each cpu, but
the protocols will share the msix vector.

Given the elimination of the nvme and fcp io channels, the module
parameters will be removed.  A new parameter, lpfc_hdw_queue is added which
allows the wq/cq pair allocation per cpu to be overridden and allocated to
lesser value. If lpfc_hdw_queue is zero, the number of pairs allocated will
be based on the number of cpus. If non-zero, the parameter specifies the
number of queues to allocate. At this time, the maximum non-zero value is
64.

To manage this new paradigm, a new hardware queue structure is created to
track queue activity and relationships.

As MSIX vector allocation must be known before setting up the
relationships, msix allocation now occurs before queue datastructures are
allocated. If the number of vectors allocated is less than the desired
hardware queues, the hardware queue counts will be reduced to the number of
vectors

Signed-off-by: default avatarDick Kennedy <dick.kennedy@broadcom.com>
Signed-off-by: default avatarJames Smart <jsmart2021@gmail.com>
Reviewed-by: default avatarHannes Reinecke <hare@suse.com>
Signed-off-by: default avatarMartin K. Petersen <martin.petersen@oracle.com>
parent 7370d10a

drivers/scsi/lpfc/lpfc.h

+1 −3
Original line number Diff line number Diff line
@@ -810,11 +810,10 @@ struct lpfc_hba { 
	uint32_t cfg_auto_imax;

	uint32_t cfg_fcp_imax;

	uint32_t cfg_fcp_cpu_map;

	uint32_t cfg_fcp_io_channel;

	uint32_t cfg_hdw_queue;

	uint32_t cfg_suppress_rsp;

	uint32_t cfg_nvme_oas;

	uint32_t cfg_nvme_embed_cmd;

	uint32_t cfg_nvme_io_channel;

	uint32_t cfg_nvmet_mrq_post;

	uint32_t cfg_nvmet_mrq;

	uint32_t cfg_enable_nvmet;
@@ -877,7 +876,6 @@ struct lpfc_hba { 
#define LPFC_ENABLE_NVME 2

#define LPFC_ENABLE_BOTH 3

	uint32_t cfg_enable_pbde;

	uint32_t io_channel_irqs;	/* number of irqs for io channels */

	struct nvmet_fc_target_port *targetport;

	lpfc_vpd_t vpd;		/* vital product data */

drivers/scsi/lpfc/lpfc_attr.c

+21 −63
Original line number Diff line number Diff line
@@ -456,7 +456,7 @@ lpfc_nvme_info_show(struct device *dev, struct device_attribute *attr, 


	totin = 0;

	totout = 0;

	for (i = 0; i < phba->cfg_nvme_io_channel; i++) {

	for (i = 0; i < phba->cfg_hdw_queue; i++) {

		cstat = &lport->cstat[i];

		tot = atomic_read(&cstat->fc4NvmeIoCmpls);

		totin += tot;
@@ -4909,7 +4909,7 @@ lpfc_fcp_imax_store(struct device *dev, struct device_attribute *attr, 
	phba->cfg_fcp_imax = (uint32_t)val;

	phba->initial_imax = phba->cfg_fcp_imax;



	for (i = 0; i < phba->io_channel_irqs; i += LPFC_MAX_EQ_DELAY_EQID_CNT)

	for (i = 0; i < phba->cfg_hdw_queue; i += LPFC_MAX_EQ_DELAY_EQID_CNT)

		lpfc_modify_hba_eq_delay(phba, i, LPFC_MAX_EQ_DELAY_EQID_CNT,

					 val);
@@ -5398,41 +5398,23 @@ LPFC_ATTR_RW(nvme_embed_cmd, 1, 0, 2, 
	     "Embed NVME Command in WQE");



/*

 * lpfc_fcp_io_channel: Set the number of FCP IO channels the driver

 * will advertise it supports to the SCSI layer. This also will map to

 * the number of WQs the driver will create.

 *

 *      0    = Configure the number of io channels to the number of active CPUs.

 *      1,32 = Manually specify how many io channels to use.

 *

 * Value range is [0,32]. Default value is 4.

 */

LPFC_ATTR_R(fcp_io_channel,

	    LPFC_FCP_IO_CHAN_DEF,

	    LPFC_HBA_IO_CHAN_MIN, LPFC_HBA_IO_CHAN_MAX,

	    "Set the number of FCP I/O channels");



/*

 * lpfc_nvme_io_channel: Set the number of IO hardware queues the driver

 * will advertise it supports to the NVME layer. This also will map to

 * the number of WQs the driver will create.

 *

 * This module parameter is valid when lpfc_enable_fc4_type is set

 * to support NVME.

 * lpfc_hdw_queue: Set the number of IO channels the driver

 * will advertise it supports to the NVME and  SCSI layers. This also

 * will map to the number of EQ/CQ/WQs the driver will create.

 *

 * The NVME Layer will try to create this many, plus 1 administrative

 * hardware queue. The administrative queue will always map to WQ 0

 * A hardware IO queue maps (qidx) to a specific driver WQ.

 *

 *      0    = Configure the number of io channels to the number of active CPUs.

 *      1,32 = Manually specify how many io channels to use.

 *      0    = Configure the number of hdw queues to the number of active CPUs.

 *      1,64 = Manually specify how many hdw queues to use.

 *

 * Value range is [0,32]. Default value is 0.

 * Value range is [0,64]. Default value is 0.

 */

LPFC_ATTR_R(nvme_io_channel,

	    LPFC_NVME_IO_CHAN_DEF,

	    LPFC_HBA_IO_CHAN_MIN, LPFC_HBA_IO_CHAN_MAX,

	    "Set the number of NVME I/O channels");

LPFC_ATTR_R(hdw_queue,

	    LPFC_HBA_HDWQ_DEF,

	    LPFC_HBA_HDWQ_MIN, LPFC_HBA_HDWQ_MAX,

	    "Set the number of I/O Hardware Queues");



/*

# lpfc_enable_hba_reset: Allow or prevent HBA resets to the hardware.
@@ -5727,9 +5709,8 @@ struct device_attribute *lpfc_hba_attrs[] = { 
	&dev_attr_lpfc_auto_imax,

	&dev_attr_lpfc_fcp_imax,

	&dev_attr_lpfc_fcp_cpu_map,

	&dev_attr_lpfc_fcp_io_channel,

	&dev_attr_lpfc_hdw_queue,

	&dev_attr_lpfc_suppress_rsp,

	&dev_attr_lpfc_nvme_io_channel,

	&dev_attr_lpfc_nvmet_mrq,

	&dev_attr_lpfc_nvmet_mrq_post,

	&dev_attr_lpfc_nvme_enable_fb,
@@ -6806,8 +6787,7 @@ lpfc_get_cfgparam(struct lpfc_hba *phba) 
	/* Initialize first burst. Target vs Initiator are different. */

	lpfc_nvme_enable_fb_init(phba, lpfc_nvme_enable_fb);

	lpfc_nvmet_fb_size_init(phba, lpfc_nvmet_fb_size);

	lpfc_fcp_io_channel_init(phba, lpfc_fcp_io_channel);

	lpfc_nvme_io_channel_init(phba, lpfc_nvme_io_channel);

	lpfc_hdw_queue_init(phba, lpfc_hdw_queue);

	lpfc_enable_bbcr_init(phba, lpfc_enable_bbcr);

	lpfc_enable_dpp_init(phba, lpfc_enable_dpp);
@@ -6829,21 +6809,8 @@ lpfc_get_cfgparam(struct lpfc_hba *phba) 
	phba->cfg_enable_pbde = 0;



	/* A value of 0 means use the number of CPUs found in the system */

	if (phba->cfg_fcp_io_channel == 0)

		phba->cfg_fcp_io_channel = phba->sli4_hba.num_present_cpu;

	if (phba->cfg_nvme_io_channel == 0)

		phba->cfg_nvme_io_channel = phba->sli4_hba.num_present_cpu;



	if (phba->cfg_enable_fc4_type == LPFC_ENABLE_NVME)

		phba->cfg_fcp_io_channel = 0;



	if (phba->cfg_enable_fc4_type == LPFC_ENABLE_FCP)

		phba->cfg_nvme_io_channel = 0;



	if (phba->cfg_fcp_io_channel > phba->cfg_nvme_io_channel)

		phba->io_channel_irqs = phba->cfg_fcp_io_channel;

	else

		phba->io_channel_irqs = phba->cfg_nvme_io_channel;

	if (phba->cfg_hdw_queue == 0)

		phba->cfg_hdw_queue = phba->sli4_hba.num_present_cpu;



	phba->cfg_soft_wwnn = 0L;

	phba->cfg_soft_wwpn = 0L;
@@ -6884,16 +6851,12 @@ lpfc_get_cfgparam(struct lpfc_hba *phba) 
void

lpfc_nvme_mod_param_dep(struct lpfc_hba *phba)

{

	if (phba->cfg_nvme_io_channel > phba->sli4_hba.num_present_cpu)

		phba->cfg_nvme_io_channel = phba->sli4_hba.num_present_cpu;



	if (phba->cfg_fcp_io_channel > phba->sli4_hba.num_present_cpu)

		phba->cfg_fcp_io_channel = phba->sli4_hba.num_present_cpu;

	if (phba->cfg_hdw_queue > phba->sli4_hba.num_present_cpu)

		phba->cfg_hdw_queue = phba->sli4_hba.num_present_cpu;



	if (phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME &&

	    phba->nvmet_support) {

		phba->cfg_enable_fc4_type &= ~LPFC_ENABLE_FCP;

		phba->cfg_fcp_io_channel = 0;



		lpfc_printf_log(phba, KERN_INFO, LOG_NVME_DISC,

				"6013 %s x%x fb_size x%x, fb_max x%x\n",
@@ -6910,11 +6873,11 @@ lpfc_nvme_mod_param_dep(struct lpfc_hba *phba) 
		}



		if (!phba->cfg_nvmet_mrq)

			phba->cfg_nvmet_mrq = phba->cfg_nvme_io_channel;

			phba->cfg_nvmet_mrq = phba->cfg_hdw_queue;



		/* Adjust lpfc_nvmet_mrq to avoid running out of WQE slots */

		if (phba->cfg_nvmet_mrq > phba->cfg_nvme_io_channel) {

			phba->cfg_nvmet_mrq = phba->cfg_nvme_io_channel;

		if (phba->cfg_nvmet_mrq > phba->cfg_hdw_queue) {

			phba->cfg_nvmet_mrq = phba->cfg_hdw_queue;

			lpfc_printf_log(phba, KERN_ERR, LOG_NVME_DISC,

					"6018 Adjust lpfc_nvmet_mrq to %d\n",

					phba->cfg_nvmet_mrq);
@@ -6928,11 +6891,6 @@ lpfc_nvme_mod_param_dep(struct lpfc_hba *phba) 
		phba->cfg_nvmet_mrq = LPFC_NVMET_MRQ_OFF;

		phba->cfg_nvmet_fb_size = 0;

	}



	if (phba->cfg_fcp_io_channel > phba->cfg_nvme_io_channel)

		phba->io_channel_irqs = phba->cfg_fcp_io_channel;

	else

		phba->io_channel_irqs = phba->cfg_nvme_io_channel;

}



/**

drivers/scsi/lpfc/lpfc_debugfs.c

+67 −85
Original line number Diff line number Diff line
@@ -919,13 +919,13 @@ lpfc_debugfs_nvmestat_data(struct lpfc_vport *vport, char *buf, int size) 
				atomic_read(&lport->fc4NvmeLsRequests),

				atomic_read(&lport->fc4NvmeLsCmpls));



		if (phba->cfg_nvme_io_channel < 32)

			maxch = phba->cfg_nvme_io_channel;

		if (phba->cfg_hdw_queue < LPFC_HBA_HDWQ_MAX)

			maxch = phba->cfg_hdw_queue;

		else

			maxch = 32;

			maxch = LPFC_HBA_HDWQ_MAX;

		totin = 0;

		totout = 0;

		for (i = 0; i < phba->cfg_nvme_io_channel; i++) {

		for (i = 0; i < phba->cfg_hdw_queue; i++) {

			cstat = &lport->cstat[i];

			tot = atomic_read(&cstat->fc4NvmeIoCmpls);

			totin += tot;
@@ -3182,22 +3182,24 @@ lpfc_idiag_wqs_for_cq(struct lpfc_hba *phba, char *wqtype, char *pbuffer, 
	struct lpfc_queue *qp;

	int qidx;



	for (qidx = 0; qidx < phba->cfg_fcp_io_channel; qidx++) {

		qp = phba->sli4_hba.fcp_wq[qidx];

	for (qidx = 0; qidx < phba->cfg_hdw_queue; qidx++) {

		qp = phba->sli4_hba.hdwq[qidx].fcp_wq;

		if (qp->assoc_qid != cq_id)

			continue;

		*len = __lpfc_idiag_print_wq(qp, wqtype, pbuffer, *len);

		if (*len >= max_cnt)

			return 1;

	}

	for (qidx = 0; qidx < phba->cfg_nvme_io_channel; qidx++) {

		qp = phba->sli4_hba.nvme_wq[qidx];

	if (phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME) {

		for (qidx = 0; qidx < phba->cfg_hdw_queue; qidx++) {

			qp = phba->sli4_hba.hdwq[qidx].nvme_wq;

			if (qp->assoc_qid != cq_id)

				continue;

			*len = __lpfc_idiag_print_wq(qp, wqtype, pbuffer, *len);

			if (*len >= max_cnt)

				return 1;

		}

	}

	return 0;

}
@@ -3262,8 +3264,8 @@ lpfc_idiag_cqs_for_eq(struct lpfc_hba *phba, char *pbuffer, 
	struct lpfc_queue *qp;

	int qidx, rc;



	for (qidx = 0; qidx < phba->cfg_fcp_io_channel; qidx++) {

		qp = phba->sli4_hba.fcp_cq[qidx];

	for (qidx = 0; qidx < phba->cfg_hdw_queue; qidx++) {

		qp = phba->sli4_hba.hdwq[qidx].fcp_cq;

		if (qp->assoc_qid != eq_id)

			continue;
@@ -3281,8 +3283,9 @@ lpfc_idiag_cqs_for_eq(struct lpfc_hba *phba, char *pbuffer, 
			return 1;

	}



	for (qidx = 0; qidx < phba->cfg_nvme_io_channel; qidx++) {

		qp = phba->sli4_hba.nvme_cq[qidx];

	if (phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME) {

		for (qidx = 0; qidx < phba->cfg_hdw_queue; qidx++) {

			qp = phba->sli4_hba.hdwq[qidx].nvme_cq;

			if (qp->assoc_qid != eq_id)

				continue;
@@ -3299,6 +3302,7 @@ lpfc_idiag_cqs_for_eq(struct lpfc_hba *phba, char *pbuffer, 
			if (rc)

				return 1;

		}

	}



	if ((eqidx < phba->cfg_nvmet_mrq) && phba->nvmet_support) {

		/* NVMET CQset */
@@ -3387,19 +3391,19 @@ lpfc_idiag_queinfo_read(struct file *file, char __user *buf, size_t nbytes, 
	spin_lock_irq(&phba->hbalock);



	/* Fast-path event queue */

	if (phba->sli4_hba.hba_eq && phba->io_channel_irqs) {

	if (phba->sli4_hba.hdwq && phba->cfg_hdw_queue) {



		x = phba->lpfc_idiag_last_eq;

		phba->lpfc_idiag_last_eq++;

		if (phba->lpfc_idiag_last_eq >= phba->io_channel_irqs)

		if (phba->lpfc_idiag_last_eq >= phba->cfg_hdw_queue)

			phba->lpfc_idiag_last_eq = 0;



		len += snprintf(pbuffer + len, LPFC_QUE_INFO_GET_BUF_SIZE - len,

					"EQ %d out of %d HBA EQs\n",

					x, phba->io_channel_irqs);

					x, phba->cfg_hdw_queue);



		/* Fast-path EQ */

		qp = phba->sli4_hba.hba_eq[x];

		qp = phba->sli4_hba.hdwq[x].hba_eq;

		if (!qp)

			goto out;
@@ -3691,9 +3695,9 @@ lpfc_idiag_queacc_write(struct file *file, const char __user *buf, 
	switch (quetp) {

	case LPFC_IDIAG_EQ:

		/* HBA event queue */

		if (phba->sli4_hba.hba_eq) {

			for (qidx = 0; qidx < phba->io_channel_irqs; qidx++) {

				qp = phba->sli4_hba.hba_eq[qidx];

		if (phba->sli4_hba.hdwq) {

			for (qidx = 0; qidx < phba->cfg_hdw_queue; qidx++) {

				qp = phba->sli4_hba.hdwq[qidx].hba_eq;

				if (qp && qp->queue_id == queid) {

					/* Sanity check */

					rc = lpfc_idiag_que_param_check(qp,
@@ -3742,10 +3746,10 @@ lpfc_idiag_queacc_write(struct file *file, const char __user *buf, 
			goto pass_check;

		}

		/* FCP complete queue */

		if (phba->sli4_hba.fcp_cq) {

			for (qidx = 0; qidx < phba->cfg_fcp_io_channel;

		if (phba->sli4_hba.hdwq) {

			for (qidx = 0; qidx < phba->cfg_hdw_queue;

								qidx++) {

				qp = phba->sli4_hba.fcp_cq[qidx];

				qp = phba->sli4_hba.hdwq[qidx].fcp_cq;

				if (qp && qp->queue_id == queid) {

					/* Sanity check */

					rc = lpfc_idiag_que_param_check(
@@ -3758,23 +3762,20 @@ lpfc_idiag_queacc_write(struct file *file, const char __user *buf, 
			}

		}

		/* NVME complete queue */

		if (phba->sli4_hba.nvme_cq) {

		if (phba->sli4_hba.hdwq) {

			qidx = 0;

			do {

				if (phba->sli4_hba.nvme_cq[qidx] &&

				    phba->sli4_hba.nvme_cq[qidx]->queue_id ==

				    queid) {

				qp = phba->sli4_hba.hdwq[qidx].nvme_cq;

				if (qp && qp->queue_id == queid) {

					/* Sanity check */

					rc = lpfc_idiag_que_param_check(

						phba->sli4_hba.nvme_cq[qidx],

						index, count);

						qp, index, count);

					if (rc)

						goto error_out;

					idiag.ptr_private =

						phba->sli4_hba.nvme_cq[qidx];

					idiag.ptr_private = qp;

					goto pass_check;

				}

			} while (++qidx < phba->cfg_nvme_io_channel);

			} while (++qidx < phba->cfg_hdw_queue);

		}

		goto error_out;

		break;
@@ -3815,11 +3816,11 @@ lpfc_idiag_queacc_write(struct file *file, const char __user *buf, 
			idiag.ptr_private = phba->sli4_hba.nvmels_wq;

			goto pass_check;

		}

		/* FCP work queue */

		if (phba->sli4_hba.fcp_wq) {

			for (qidx = 0; qidx < phba->cfg_fcp_io_channel;

								qidx++) {

				qp = phba->sli4_hba.fcp_wq[qidx];



		if (phba->sli4_hba.hdwq) {

			/* FCP/SCSI work queue */

			for (qidx = 0; qidx < phba->cfg_hdw_queue; qidx++) {

				qp = phba->sli4_hba.hdwq[qidx].fcp_wq;

				if (qp && qp->queue_id == queid) {

					/* Sanity check */

					rc = lpfc_idiag_que_param_check(
@@ -3830,12 +3831,9 @@ lpfc_idiag_queacc_write(struct file *file, const char __user *buf, 
					goto pass_check;

				}

			}

		}

			/* NVME work queue */

		if (phba->sli4_hba.nvme_wq) {

			for (qidx = 0; qidx < phba->cfg_nvme_io_channel;

								qidx++) {

				qp = phba->sli4_hba.nvme_wq[qidx];

			for (qidx = 0; qidx < phba->cfg_hdw_queue; qidx++) {

				qp = phba->sli4_hba.hdwq[qidx].nvme_wq;

				if (qp && qp->queue_id == queid) {

					/* Sanity check */

					rc = lpfc_idiag_que_param_check(
@@ -3848,26 +3846,6 @@ lpfc_idiag_queacc_write(struct file *file, const char __user *buf, 
			}

		}



		/* NVME work queues */

		if (phba->sli4_hba.nvme_wq) {

			for (qidx = 0; qidx < phba->cfg_nvme_io_channel;

				qidx++) {

				if (!phba->sli4_hba.nvme_wq[qidx])

					continue;

				if (phba->sli4_hba.nvme_wq[qidx]->queue_id ==

				    queid) {

					/* Sanity check */

					rc = lpfc_idiag_que_param_check(

						phba->sli4_hba.nvme_wq[qidx],

						index, count);

					if (rc)

						goto error_out;

					idiag.ptr_private =

						phba->sli4_hba.nvme_wq[qidx];

					goto pass_check;

				}

			}

		}

		goto error_out;

		break;

	case LPFC_IDIAG_RQ:
@@ -5784,11 +5762,13 @@ lpfc_debug_dump_all_queues(struct lpfc_hba *phba) 
	lpfc_debug_dump_wq(phba, DUMP_ELS, 0);

	lpfc_debug_dump_wq(phba, DUMP_NVMELS, 0);



	for (idx = 0; idx < phba->cfg_fcp_io_channel; idx++)

	for (idx = 0; idx < phba->cfg_hdw_queue; idx++)

		lpfc_debug_dump_wq(phba, DUMP_FCP, idx);



	for (idx = 0; idx < phba->cfg_nvme_io_channel; idx++)

	if (phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME) {

		for (idx = 0; idx < phba->cfg_hdw_queue; idx++)

			lpfc_debug_dump_wq(phba, DUMP_NVME, idx);

	}



	lpfc_debug_dump_hdr_rq(phba);

	lpfc_debug_dump_dat_rq(phba);
@@ -5799,15 +5779,17 @@ lpfc_debug_dump_all_queues(struct lpfc_hba *phba) 
	lpfc_debug_dump_cq(phba, DUMP_ELS, 0);

	lpfc_debug_dump_cq(phba, DUMP_NVMELS, 0);



	for (idx = 0; idx < phba->cfg_fcp_io_channel; idx++)

	for (idx = 0; idx < phba->cfg_hdw_queue; idx++)

		lpfc_debug_dump_cq(phba, DUMP_FCP, idx);



	for (idx = 0; idx < phba->cfg_nvme_io_channel; idx++)

	if (phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME) {

		for (idx = 0; idx < phba->cfg_hdw_queue; idx++)

			lpfc_debug_dump_cq(phba, DUMP_NVME, idx);

	}



	/*

	 * Dump Event Queues (EQs)

	 */

	for (idx = 0; idx < phba->io_channel_irqs; idx++)

	for (idx = 0; idx < phba->cfg_hdw_queue; idx++)

		lpfc_debug_dump_hba_eq(phba, idx);

}

drivers/scsi/lpfc/lpfc_debugfs.h

+33 −32
Original line number Diff line number Diff line
@@ -410,10 +410,10 @@ lpfc_debug_dump_wq(struct lpfc_hba *phba, int qtype, int wqidx) 
	char *qtypestr;



	if (qtype == DUMP_FCP) {

		wq = phba->sli4_hba.fcp_wq[wqidx];

		wq = phba->sli4_hba.hdwq[wqidx].fcp_wq;

		qtypestr = "FCP";

	} else if (qtype == DUMP_NVME) {

		wq = phba->sli4_hba.nvme_wq[wqidx];

		wq = phba->sli4_hba.hdwq[wqidx].nvme_wq;

		qtypestr = "NVME";

	} else if (qtype == DUMP_MBX) {

		wq = phba->sli4_hba.mbx_wq;
@@ -454,14 +454,15 @@ lpfc_debug_dump_cq(struct lpfc_hba *phba, int qtype, int wqidx) 
	int eqidx;



	/* fcp/nvme wq and cq are 1:1, thus same indexes */

	eq = NULL;



	if (qtype == DUMP_FCP) {

		wq = phba->sli4_hba.fcp_wq[wqidx];

		cq = phba->sli4_hba.fcp_cq[wqidx];

		wq = phba->sli4_hba.hdwq[wqidx].fcp_wq;

		cq = phba->sli4_hba.hdwq[wqidx].fcp_cq;

		qtypestr = "FCP";

	} else if (qtype == DUMP_NVME) {

		wq = phba->sli4_hba.nvme_wq[wqidx];

		cq = phba->sli4_hba.nvme_cq[wqidx];

		wq = phba->sli4_hba.hdwq[wqidx].nvme_wq;

		cq = phba->sli4_hba.hdwq[wqidx].nvme_cq;

		qtypestr = "NVME";

	} else if (qtype == DUMP_MBX) {

		wq = phba->sli4_hba.mbx_wq;
@@ -478,17 +479,17 @@ lpfc_debug_dump_cq(struct lpfc_hba *phba, int qtype, int wqidx) 
	} else

		return;



	for (eqidx = 0; eqidx < phba->io_channel_irqs; eqidx++) {

		if (cq->assoc_qid == phba->sli4_hba.hba_eq[eqidx]->queue_id)

	for (eqidx = 0; eqidx < phba->cfg_hdw_queue; eqidx++) {

		eq = phba->sli4_hba.hdwq[eqidx].hba_eq;

		if (cq->assoc_qid == eq->queue_id)

			break;

	}

	if (eqidx == phba->io_channel_irqs) {

	if (eqidx == phba->cfg_hdw_queue) {

		pr_err("Couldn't find EQ for CQ. Using EQ[0]\n");

		eqidx = 0;

		eq = phba->sli4_hba.hdwq[0].hba_eq;

	}



	eq = phba->sli4_hba.hba_eq[eqidx];



	if (qtype == DUMP_FCP || qtype == DUMP_NVME)

		pr_err("%s CQ: WQ[Idx:%d|Qid%d]->CQ[Idx%d|Qid%d]"

			"->EQ[Idx:%d|Qid:%d]:\n",
@@ -516,7 +517,7 @@ lpfc_debug_dump_hba_eq(struct lpfc_hba *phba, int qidx) 
{

	struct lpfc_queue *qp;



	qp = phba->sli4_hba.hba_eq[qidx];

	qp = phba->sli4_hba.hdwq[qidx].hba_eq;



	pr_err("EQ[Idx:%d|Qid:%d]\n", qidx, qp->queue_id);
@@ -564,21 +565,21 @@ lpfc_debug_dump_wq_by_id(struct lpfc_hba *phba, int qid) 
{

	int wq_idx;



	for (wq_idx = 0; wq_idx < phba->cfg_fcp_io_channel; wq_idx++)

		if (phba->sli4_hba.fcp_wq[wq_idx]->queue_id == qid)

	for (wq_idx = 0; wq_idx < phba->cfg_hdw_queue; wq_idx++)

		if (phba->sli4_hba.hdwq[wq_idx].fcp_wq->queue_id == qid)

			break;

	if (wq_idx < phba->cfg_fcp_io_channel) {

	if (wq_idx < phba->cfg_hdw_queue) {

		pr_err("FCP WQ[Idx:%d|Qid:%d]\n", wq_idx, qid);

		lpfc_debug_dump_q(phba->sli4_hba.fcp_wq[wq_idx]);

		lpfc_debug_dump_q(phba->sli4_hba.hdwq[wq_idx].fcp_wq);

		return;

	}



	for (wq_idx = 0; wq_idx < phba->cfg_nvme_io_channel; wq_idx++)

		if (phba->sli4_hba.nvme_wq[wq_idx]->queue_id == qid)

	for (wq_idx = 0; wq_idx < phba->cfg_hdw_queue; wq_idx++)

		if (phba->sli4_hba.hdwq[wq_idx].nvme_wq->queue_id == qid)

			break;

	if (wq_idx < phba->cfg_nvme_io_channel) {

	if (wq_idx < phba->cfg_hdw_queue) {

		pr_err("NVME WQ[Idx:%d|Qid:%d]\n", wq_idx, qid);

		lpfc_debug_dump_q(phba->sli4_hba.nvme_wq[wq_idx]);

		lpfc_debug_dump_q(phba->sli4_hba.hdwq[wq_idx].nvme_wq);

		return;

	}
@@ -646,23 +647,23 @@ lpfc_debug_dump_cq_by_id(struct lpfc_hba *phba, int qid) 
{

	int cq_idx;



	for (cq_idx = 0; cq_idx < phba->cfg_fcp_io_channel; cq_idx++)

		if (phba->sli4_hba.fcp_cq[cq_idx]->queue_id == qid)

	for (cq_idx = 0; cq_idx < phba->cfg_hdw_queue; cq_idx++)

		if (phba->sli4_hba.hdwq[cq_idx].fcp_cq->queue_id == qid)

			break;



	if (cq_idx < phba->cfg_fcp_io_channel) {

	if (cq_idx < phba->cfg_hdw_queue) {

		pr_err("FCP CQ[Idx:%d|Qid:%d]\n", cq_idx, qid);

		lpfc_debug_dump_q(phba->sli4_hba.fcp_cq[cq_idx]);

		lpfc_debug_dump_q(phba->sli4_hba.hdwq[cq_idx].fcp_cq);

		return;

	}



	for (cq_idx = 0; cq_idx < phba->cfg_nvme_io_channel; cq_idx++)

		if (phba->sli4_hba.nvme_cq[cq_idx]->queue_id == qid)

	for (cq_idx = 0; cq_idx < phba->cfg_hdw_queue; cq_idx++)

		if (phba->sli4_hba.hdwq[cq_idx].nvme_cq->queue_id == qid)

			break;



	if (cq_idx < phba->cfg_nvme_io_channel) {

	if (cq_idx < phba->cfg_hdw_queue) {

		pr_err("NVME CQ[Idx:%d|Qid:%d]\n", cq_idx, qid);

		lpfc_debug_dump_q(phba->sli4_hba.nvme_cq[cq_idx]);

		lpfc_debug_dump_q(phba->sli4_hba.hdwq[cq_idx].nvme_cq);

		return;

	}
@@ -697,13 +698,13 @@ lpfc_debug_dump_eq_by_id(struct lpfc_hba *phba, int qid) 
{

	int eq_idx;



	for (eq_idx = 0; eq_idx < phba->io_channel_irqs; eq_idx++)

		if (phba->sli4_hba.hba_eq[eq_idx]->queue_id == qid)

	for (eq_idx = 0; eq_idx < phba->cfg_hdw_queue; eq_idx++)

		if (phba->sli4_hba.hdwq[eq_idx].hba_eq->queue_id == qid)

			break;



	if (eq_idx < phba->io_channel_irqs) {

	if (eq_idx < phba->cfg_hdw_queue) {

		printk(KERN_ERR "FCP EQ[Idx:%d|Qid:%d]\n", eq_idx, qid);

		lpfc_debug_dump_q(phba->sli4_hba.hba_eq[eq_idx]);

		lpfc_debug_dump_q(phba->sli4_hba.hdwq[eq_idx].hba_eq);

		return;

	}

}

drivers/scsi/lpfc/lpfc_init.c

+178 −311

File changed.

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