Commit cda13dd1 authored by Paul Gortmaker's avatar Paul Gortmaker Committed by Kumar Gala
Browse files

[POWERPC] 83xx: Clean up / convert mpc83xx board DTS files to v1 format. 



This patch converts the remaining 83xx boards to the dts-v1 format.
This includes the mpc8313_rdb, mpc832x_mds, mpc8323_rdb, mpc8349emitx,
mpc8349emitxgp and the mpc836x_mds.

The mpc8315_rdb mpc834x_mds, mpc837[789]_*, and sbc8349 were already
dts-v1 and only undergo minor changes for the sake of formatting
consistency across the whole group of boards; i.e.  the idea being
that you can do a "diff -u board_A.dts board_B.dts" and see something
meaningful.

The general rule I've applied is that entries for values normally
parsed by humans are left in decimal (i.e. IRQ, cache size, clock
rates, basic counts and indexes) and all other data (i.e. reg and
ranges, IRQ flags etc.) remain in hex.

I've used dtc to confirm that the output prior to this changeset
matches the output after this changeset is applied for all boards.

Signed-off-by: default avatarPaul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: default avatarKumar Gala <galak@kernel.crashing.org>
parent a6f71745

arch/powerpc/boot/dts/mpc8313erdb.dts

+77 −75
Original line number Diff line number Diff line
@@ -9,6 +9,8 @@ 
 * option) any later version.

 */



/dts-v1/;



/ {

	model = "MPC8313ERDB";

	compatible = "MPC8313ERDB", "MPC831xRDB", "MPC83xxRDB";
@@ -29,11 +31,11 @@ 


		PowerPC,8313@0 {

			device_type = "cpu";

			reg = <0>;

			d-cache-line-size = <20>;	// 32 bytes

			i-cache-line-size = <20>;	// 32 bytes

			d-cache-size = <4000>;		// L1, 16K

			i-cache-size = <4000>;		// L1, 16K

			reg = <0x0>;

			d-cache-line-size = <32>;

			i-cache-line-size = <32>;

			d-cache-size = <16384>;

			i-cache-size = <16384>;

			timebase-frequency = <0>;	// from bootloader

			bus-frequency = <0>;		// from bootloader

			clock-frequency = <0>;		// from bootloader
@@ -42,30 +44,30 @@ 


	memory {

		device_type = "memory";

		reg = <00000000 08000000>;	// 128MB at 0

		reg = <0x00000000 0x08000000>;	// 128MB at 0

	};



	localbus@e0005000 {

		#address-cells = <2>;

		#size-cells = <1>;

		compatible = "fsl,mpc8313-elbc", "fsl,elbc", "simple-bus";

		reg = <e0005000 1000>;

		interrupts = <d#77 8>;

		reg = <0xe0005000 0x1000>;

		interrupts = <77 0x8>;

		interrupt-parent = <&ipic>;



		// CS0 and CS1 are swapped when

		// booting from nand, but the

		// addresses are the same.

		ranges = <0 0 fe000000 00800000

		          1 0 e2800000 00008000

		          2 0 f0000000 00020000

		          3 0 fa000000 00008000>;

		ranges = <0x0 0x0 0xfe000000 0x00800000

		          0x1 0x0 0xe2800000 0x00008000

		          0x2 0x0 0xf0000000 0x00020000

		          0x3 0x0 0xfa000000 0x00008000>;



		flash@0,0 {

			#address-cells = <1>;

			#size-cells = <1>;

			compatible = "cfi-flash";

			reg = <0 0 800000>;

			reg = <0x0 0x0 0x800000>;

			bank-width = <2>;

			device-width = <1>;

		};
@@ -75,19 +77,19 @@ 
			#size-cells = <1>;

			compatible = "fsl,mpc8313-fcm-nand",

			             "fsl,elbc-fcm-nand";

			reg = <1 0 2000>;

			reg = <0x1 0x0 0x2000>;



			u-boot@0 {

				reg = <0 100000>;

				reg = <0x0 0x100000>;

				read-only;

			};



			kernel@100000 {

				reg = <100000 300000>;

				reg = <0x100000 0x300000>;

			};



			fs@400000 {

				reg = <400000 1c00000>;

				reg = <0x400000 0x1c00000>;

			};

		};

	};
@@ -97,14 +99,14 @@ 
		#size-cells = <1>;

		device_type = "soc";

		compatible = "simple-bus";

		ranges = <0 e0000000 00100000>;

		reg = <e0000000 00000200>;

		ranges = <0x0 0xe0000000 0x00100000>;

		reg = <0xe0000000 0x00000200>;

		bus-frequency = <0>;



		wdt@200 {

			device_type = "watchdog";

			compatible = "mpc83xx_wdt";

			reg = <200 100>;

			reg = <0x200 0x100>;

		};



		i2c@3000 {
@@ -112,8 +114,8 @@ 
			#size-cells = <0>;

			cell-index = <0>;

			compatible = "fsl-i2c";

			reg = <3000 100>;

			interrupts = <e 8>;

			reg = <0x3000 0x100>;

			interrupts = <14 0x8>;

			interrupt-parent = <&ipic>;

			dfsrr;

		};
@@ -123,8 +125,8 @@ 
			#size-cells = <0>;

			cell-index = <1>;

			compatible = "fsl-i2c";

			reg = <3100 100>;

			interrupts = <f 8>;

			reg = <0x3100 0x100>;

			interrupts = <15 0x8>;

			interrupt-parent = <&ipic>;

			dfsrr;

		};
@@ -132,8 +134,8 @@ 
		spi@7000 {

			cell-index = <0>;

			compatible = "fsl,spi";

			reg = <7000 1000>;

			interrupts = <10 8>;

			reg = <0x7000 0x1000>;

			interrupts = <16 0x8>;

			interrupt-parent = <&ipic>;

			mode = "cpu";

		};
@@ -141,11 +143,11 @@ 
		/* phy type (ULPI, UTMI, UTMI_WIDE, SERIAL) */

		usb@23000 {

			compatible = "fsl-usb2-dr";

			reg = <23000 1000>;

			reg = <0x23000 0x1000>;

			#address-cells = <1>;

			#size-cells = <0>;

			interrupt-parent = <&ipic>;

			interrupts = <26 8>;

			interrupts = <38 0x8>;

			phy_type = "utmi_wide";

		};
@@ -153,17 +155,17 @@ 
			#address-cells = <1>;

			#size-cells = <0>;

			compatible = "fsl,gianfar-mdio";

			reg = <24520 20>;

			reg = <0x24520 0x20>;

			phy1: ethernet-phy@1 {

				interrupt-parent = <&ipic>;

				interrupts = <13 8>;

				reg = <1>;

				interrupts = <19 0x8>;

				reg = <0x1>;

				device_type = "ethernet-phy";

			};

			phy4: ethernet-phy@4 {

				interrupt-parent = <&ipic>;

				interrupts = <14 8>;

				reg = <4>;

				interrupts = <20 0x8>;

				reg = <0x4>;

				device_type = "ethernet-phy";

			};

		};
@@ -173,9 +175,9 @@ 
			device_type = "network";

			model = "eTSEC";

			compatible = "gianfar";

			reg = <24000 1000>;

			reg = <0x24000 0x1000>;

			local-mac-address = [ 00 00 00 00 00 00 ];

			interrupts = <25 8 24 8 23 8>;

			interrupts = <37 0x8 36 0x8 35 0x8>;

			interrupt-parent = <&ipic>;

			phy-handle = < &phy1 >;

		};
@@ -185,9 +187,9 @@ 
			device_type = "network";

			model = "eTSEC";

			compatible = "gianfar";

			reg = <25000 1000>;

			reg = <0x25000 0x1000>;

			local-mac-address = [ 00 00 00 00 00 00 ];

			interrupts = <22 8 21 8 20 8>;

			interrupts = <34 0x8 33 0x8 32 0x8>;

			interrupt-parent = <&ipic>;

			phy-handle = < &phy4 >;

		};
@@ -196,9 +198,9 @@ 
			cell-index = <0>;

			device_type = "serial";

			compatible = "ns16550";

			reg = <4500 100>;

			reg = <0x4500 0x100>;

			clock-frequency = <0>;

			interrupts = <9 8>;

			interrupts = <9 0x8>;

			interrupt-parent = <&ipic>;

		};
@@ -206,9 +208,9 @@ 
			cell-index = <1>;

			device_type = "serial";

			compatible = "ns16550";

			reg = <4600 100>;

			reg = <0x4600 0x100>;

			clock-frequency = <0>;

			interrupts = <a 8>;

			interrupts = <10 0x8>;

			interrupt-parent = <&ipic>;

		};
@@ -216,14 +218,14 @@ 
			device_type = "crypto";

			model = "SEC2";

			compatible = "talitos";

			reg = <30000 7000>;

			interrupts = <b 8>;

			reg = <0x30000 0x7000>;

			interrupts = <11 0x8>;

			interrupt-parent = <&ipic>;

			/* Rev. 2.2 */

			num-channels = <1>;

			channel-fifo-len = <18>;

			exec-units-mask = <0000004c>;

			descriptor-types-mask = <0122003f>;

			channel-fifo-len = <24>;

			exec-units-mask = <0x0000004c>;

			descriptor-types-mask = <0x0122003f>;

		};



		/* IPIC
@@ -236,38 +238,38 @@ 
			interrupt-controller;

			#address-cells = <0>;

			#interrupt-cells = <2>;

			reg = <700 100>;

			reg = <0x700 0x100>;

			device_type = "ipic";

		};

	};



	pci0: pci@e0008500 {

		cell-index = <1>;

		interrupt-map-mask = <f800 0 0 7>;

		interrupt-map-mask = <0xf800 0x0 0x0 0x7>;

		interrupt-map = <



				/* IDSEL 0x0E -mini PCI */

				 7000 0 0 1 &ipic 12 8

				 7000 0 0 2 &ipic 12 8

				 7000 0 0 3 &ipic 12 8

				 7000 0 0 4 &ipic 12 8

				 0x7000 0x0 0x0 0x1 &ipic 18 0x8

				 0x7000 0x0 0x0 0x2 &ipic 18 0x8

				 0x7000 0x0 0x0 0x3 &ipic 18 0x8

				 0x7000 0x0 0x0 0x4 &ipic 18 0x8



				/* IDSEL 0x0F - PCI slot */

				 7800 0 0 1 &ipic 11 8

				 7800 0 0 2 &ipic 12 8

				 7800 0 0 3 &ipic 11 8

				 7800 0 0 4 &ipic 12 8>;

				 0x7800 0x0 0x0 0x1 &ipic 17 0x8

				 0x7800 0x0 0x0 0x2 &ipic 18 0x8

				 0x7800 0x0 0x0 0x3 &ipic 17 0x8

				 0x7800 0x0 0x0 0x4 &ipic 18 0x8>;

		interrupt-parent = <&ipic>;

		interrupts = <42 8>;

		bus-range = <0 0>;

		ranges = <02000000 0 90000000 90000000 0 10000000

			  42000000 0 80000000 80000000 0 10000000

			  01000000 0 00000000 e2000000 0 00100000>;

		clock-frequency = <3f940aa>;

		interrupts = <66 0x8>;

		bus-range = <0x0 0x0>;

		ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000

			  0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000

			  0x01000000 0x0 0x00000000 0xe2000000 0x0 0x00100000>;

		clock-frequency = <66666666>;

		#interrupt-cells = <1>;

		#size-cells = <2>;

		#address-cells = <3>;

		reg = <e0008500 100>;

		reg = <0xe0008500 0x100>;

		compatible = "fsl,mpc8349-pci";

		device_type = "pci";

	};

arch/powerpc/boot/dts/mpc8315erdb.dts

+50 −50
Original line number Diff line number Diff line
@@ -30,7 +30,7 @@ 


		PowerPC,8315@0 {

			device_type = "cpu";

			reg = <0>;

			reg = <0x0>;

			d-cache-line-size = <32>;

			i-cache-line-size = <32>;

			d-cache-size = <16384>;
@@ -51,22 +51,22 @@ 
		#size-cells = <1>;

		compatible = "fsl,mpc8315-elbc", "fsl,elbc", "simple-bus";

		reg = <0xe0005000 0x1000>;

		interrupts = <77 8>;

		interrupts = <77 0x8>;

		interrupt-parent = <&ipic>;



		// CS0 and CS1 are swapped when

		// booting from nand, but the

		// addresses are the same.

		ranges = <0 0 0xfe000000 0x00800000

		          1 0 0xe0600000 0x00002000

		          2 0 0xf0000000 0x00020000

		          3 0 0xfa000000 0x00008000>;

		ranges = <0x0 0x0 0xfe000000 0x00800000

		          0x1 0x0 0xe0600000 0x00002000

		          0x2 0x0 0xf0000000 0x00020000

		          0x3 0x0 0xfa000000 0x00008000>;



		flash@0,0 {

			#address-cells = <1>;

			#size-cells = <1>;

			compatible = "cfi-flash";

			reg = <0 0 0x800000>;

			reg = <0x0 0x0 0x800000>;

			bank-width = <2>;

			device-width = <1>;

		};
@@ -76,7 +76,7 @@ 
			#size-cells = <1>;

			compatible = "fsl,mpc8315-fcm-nand",

			             "fsl,elbc-fcm-nand";

			reg = <1 0 0x2000>;

			reg = <0x1 0x0 0x2000>;



			u-boot@0 {

				reg = <0x0 0x100000>;
@@ -113,7 +113,7 @@ 
			cell-index = <0>;

			compatible = "fsl-i2c";

			reg = <0x3000 0x100>;

			interrupts = <14 8>;

			interrupts = <14 0x8>;

			interrupt-parent = <&ipic>;

			dfsrr;

			rtc@68 {
@@ -127,7 +127,7 @@ 
			cell-index = <0>;

			compatible = "fsl,spi";

			reg = <0x7000 0x1000>;

			interrupts = <16 8>;

			interrupts = <16 0x8>;

			interrupt-parent = <&ipic>;

			mode = "cpu";

		};
@@ -138,7 +138,7 @@ 
			#address-cells = <1>;

			#size-cells = <0>;

			interrupt-parent = <&ipic>;

			interrupts = <38 8>;

			interrupts = <38 0x8>;

			phy_type = "utmi";

		};
@@ -149,14 +149,14 @@ 
			reg = <0x24520 0x20>;

			phy0: ethernet-phy@0 {

				interrupt-parent = <&ipic>;

				interrupts = <20 8>;

				reg = <0>;

				interrupts = <20 0x8>;

				reg = <0x0>;

				device_type = "ethernet-phy";

			};

			phy1: ethernet-phy@1 {

				interrupt-parent = <&ipic>;

				interrupts = <19 8>;

				reg = <1>;

				interrupts = <19 0x8>;

				reg = <0x1>;

				device_type = "ethernet-phy";

			};

		};
@@ -168,7 +168,7 @@ 
			compatible = "gianfar";

			reg = <0x24000 0x1000>;

			local-mac-address = [ 00 00 00 00 00 00 ];

			interrupts = <32 8 33 8 34 8>;

			interrupts = <32 0x8 33 0x8 34 0x8>;

			interrupt-parent = <&ipic>;

			phy-handle = < &phy0 >;

		};
@@ -180,7 +180,7 @@ 
			compatible = "gianfar";

			reg = <0x25000 0x1000>;

			local-mac-address = [ 00 00 00 00 00 00 ];

			interrupts = <35 8 36 8 37 8>;

			interrupts = <35 0x8 36 0x8 37 0x8>;

			interrupt-parent = <&ipic>;

			phy-handle = < &phy1 >;

		};
@@ -191,7 +191,7 @@ 
			compatible = "ns16550";

			reg = <0x4500 0x100>;

			clock-frequency = <0>;

			interrupts = <9 8>;

			interrupts = <9 0x8>;

			interrupt-parent = <&ipic>;

		};
@@ -201,7 +201,7 @@ 
			compatible = "ns16550";

			reg = <0x4600 0x100>;

			clock-frequency = <0>;

			interrupts = <10 8>;

			interrupts = <10 0x8>;

			interrupt-parent = <&ipic>;

		};
@@ -210,7 +210,7 @@ 
			device_type = "crypto";

			compatible = "talitos";

			reg = <0x30000 0x10000>;

			interrupts = <11 8>;

			interrupts = <11 0x8>;

			interrupt-parent = <&ipic>;

			/* Rev. 3.0 geometry */

			num-channels = <4>;
@@ -223,7 +223,7 @@ 
			compatible = "fsl,mpc8315-sata", "fsl,pq-sata";

			reg = <0x18000 0x1000>;

			cell-index = <1>;

			interrupts = <44 8>;

			interrupts = <44 0x8>;

			interrupt-parent = <&ipic>;

		};
@@ -231,7 +231,7 @@ 
			compatible = "fsl,mpc8315-sata", "fsl,pq-sata";

			reg = <0x19000 0x1000>;

			cell-index = <2>;

			interrupts = <45 8>;

			interrupts = <45 0x8>;

			interrupt-parent = <&ipic>;

		};
@@ -251,28 +251,28 @@ 
	};



	pci0: pci@e0008500 {

		interrupt-map-mask = <0xf800 0 0 7>;

		interrupt-map-mask = <0xf800 0x0 0x0 0x7>;

		interrupt-map = <

				/* IDSEL 0x0E -mini PCI */

				 0x7000 0 0 1 &ipic 18 8

				 0x7000 0 0 2 &ipic 18 8

				 0x7000 0 0 3 &ipic 18 8

				 0x7000 0 0 4 &ipic 18 8

				 0x7000 0x0 0x0 0x1 &ipic 18 0x8

				 0x7000 0x0 0x0 0x2 &ipic 18 0x8

				 0x7000 0x0 0x0 0x3 &ipic 18 0x8

				 0x7000 0x0 0x0 0x4 &ipic 18 0x8



				/* IDSEL 0x0F -mini PCI */

				 0x7800 0 0 1 &ipic 17 8

				 0x7800 0 0 2 &ipic 17 8

				 0x7800 0 0 3 &ipic 17 8

				 0x7800 0 0 4 &ipic 17 8

				 0x7800 0x0 0x0 0x1 &ipic 17 0x8

				 0x7800 0x0 0x0 0x2 &ipic 17 0x8

				 0x7800 0x0 0x0 0x3 &ipic 17 0x8

				 0x7800 0x0 0x0 0x4 &ipic 17 0x8



				/* IDSEL 0x10 - PCI slot */

				 0x8000 0 0 1 &ipic 48 8

				 0x8000 0 0 2 &ipic 17 8

				 0x8000 0 0 3 &ipic 48 8

				 0x8000 0 0 4 &ipic 17 8>;

				 0x8000 0x0 0x0 0x1 &ipic 48 0x8

				 0x8000 0x0 0x0 0x2 &ipic 17 0x8

				 0x8000 0x0 0x0 0x3 &ipic 48 0x8

				 0x8000 0x0 0x0 0x4 &ipic 17 0x8>;

		interrupt-parent = <&ipic>;

		interrupts = <66 8>;

		bus-range = <0 0>;

		interrupts = <66 0x8>;

		bus-range = <0x0 0x0>;

		ranges = <0x02000000 0 0x90000000 0x90000000 0 0x10000000

			  0x42000000 0 0x80000000 0x80000000 0 0x10000000

			  0x01000000 0 0x00000000 0xe0300000 0 0x00100000>;

arch/powerpc/boot/dts/mpc832x_mds.dts

+127 −125
Original line number Diff line number Diff line
@@ -21,6 +21,8 @@ 
 * you're going by the schematic, the pin is called "P19J-K22".

 */



/dts-v1/;



/ {

	model = "MPC8323EMDS";

	compatible = "MPC8323EMDS", "MPC832xMDS", "MPC83xxMDS";
@@ -41,11 +43,11 @@ 


		PowerPC,8323@0 {

			device_type = "cpu";

			reg = <0>;

			d-cache-line-size = <20>;	// 32 bytes

			i-cache-line-size = <20>;	// 32 bytes

			d-cache-size = <4000>;		// L1, 16K

			i-cache-size = <4000>;		// L1, 16K

			reg = <0x0>;

			d-cache-line-size = <32>;	// 32 bytes

			i-cache-line-size = <32>;	// 32 bytes

			d-cache-size = <16384>;		// L1, 16K

			i-cache-size = <16384>;		// L1, 16K

			timebase-frequency = <0>;

			bus-frequency = <0>;

			clock-frequency = <0>;
@@ -54,26 +56,26 @@ 


	memory {

		device_type = "memory";

		reg = <00000000 08000000>;

		reg = <0x00000000 0x08000000>;

	};



	bcsr@f8000000 {

		device_type = "board-control";

		reg = <f8000000 8000>;

		reg = <0xf8000000 0x8000>;

	};



	soc8323@e0000000 {

		#address-cells = <1>;

		#size-cells = <1>;

		device_type = "soc";

		ranges = <0 e0000000 00100000>;

		reg = <e0000000 00000200>;

		bus-frequency = <7DE2900>;

		ranges = <0x0 0xe0000000 0x00100000>;

		reg = <0xe0000000 0x00000200>;

		bus-frequency = <132000000>;



		wdt@200 {

			device_type = "watchdog";

			compatible = "mpc83xx_wdt";

			reg = <200 100>;

			reg = <0x200 0x100>;

		};



		i2c@3000 {
@@ -81,14 +83,14 @@ 
			#size-cells = <0>;

			cell-index = <0>;

			compatible = "fsl-i2c";

			reg = <3000 100>;

			interrupts = <e 8>;

			reg = <0x3000 0x100>;

			interrupts = <14 0x8>;

			interrupt-parent = <&ipic>;

			dfsrr;



			rtc@68 {

				compatible = "dallas,ds1374";

				reg = <68>;

				reg = <0x68>;

			};

		};
@@ -96,9 +98,9 @@ 
			cell-index = <0>;

			device_type = "serial";

			compatible = "ns16550";

			reg = <4500 100>;

			reg = <0x4500 0x100>;

			clock-frequency = <0>;

			interrupts = <9 8>;

			interrupts = <9 0x8>;

			interrupt-parent = <&ipic>;

		};
@@ -106,9 +108,9 @@ 
			cell-index = <1>;

			device_type = "serial";

			compatible = "ns16550";

			reg = <4600 100>;

			reg = <0x4600 0x100>;

			clock-frequency = <0>;

			interrupts = <a 8>;

			interrupts = <10 0x8>;

			interrupt-parent = <&ipic>;

		};
@@ -116,26 +118,26 @@ 
			device_type = "crypto";

			model = "SEC2";

			compatible = "talitos";

			reg = <30000 7000>;

			interrupts = <b 8>;

			reg = <0x30000 0x7000>;

			interrupts = <11 0x8>;

			interrupt-parent = <&ipic>;

			/* Rev. 2.2 */

			num-channels = <1>;

			channel-fifo-len = <18>;

			exec-units-mask = <0000004c>;

			descriptor-types-mask = <0122003f>;

			channel-fifo-len = <24>;

			exec-units-mask = <0x0000004c>;

			descriptor-types-mask = <0x0122003f>;

		};



		ipic: pic@700 {

			interrupt-controller;

			#address-cells = <0>;

			#interrupt-cells = <2>;

			reg = <700 100>;

			reg = <0x700 0x100>;

			device_type = "ipic";

		};



		par_io@1400 {

			reg = <1400 100>;

			reg = <0x1400 0x100>;

			device_type = "par_io";

			num-ports = <7>;
@@ -144,8 +146,8 @@ 
			/* port  pin  dir  open_drain  assignment  has_irq */

					3  4  3  0  2  0  /* MDIO */

					3  5  1  0  2  0  /* MDC */

					0  d  2  0  1  0 	/* RX_CLK (CLK9) */

					3 18  2  0  1  0 	/* TX_CLK (CLK10) */

					0 13  2  0  1  0 	/* RX_CLK (CLK9) */

					3 24  2  0  1  0 	/* TX_CLK (CLK10) */

					1  0  1  0  1  0 	/* TxD0 */

					1  1  1  0  1  0 	/* TxD1 */

					1  2  1  0  1  0 	/* TxD2 */
@@ -156,30 +158,30 @@ 
					1  7  2  0  1  0 	/* RxD3 */

					1  8  2  0  1  0 	/* RX_ER */

					1  9  1  0  1  0 	/* TX_ER */

					1  a  2  0  1  0 	/* RX_DV */

					1  b  2  0  1  0 	/* COL */

					1  c  1  0  1  0 	/* TX_EN */

					1  d  2  0  1  0>;/* CRS */

					1 10  2  0  1  0 	/* RX_DV */

					1 11  2  0  1  0 	/* COL */

					1 12  1  0  1  0 	/* TX_EN */

					1 13  2  0  1  0>;	/* CRS */

			};

			pio4: ucc_pin@04 {

				pio-map = <

			/* port  pin  dir  open_drain  assignment  has_irq */

					3 1f  2  0  1  0 	/* RX_CLK (CLK7) */

					3 31  2  0  1  0 	/* RX_CLK (CLK7) */

					3  6  2  0  1  0 	/* TX_CLK (CLK8) */

					1 12  1  0  1  0 	/* TxD0 */

					1 13  1  0  1  0 	/* TxD1 */

					1 14  1  0  1  0 	/* TxD2 */

					1 15  1  0  1  0 	/* TxD3 */

					1 16  2  0  1  0 	/* RxD0 */

					1 17  2  0  1  0 	/* RxD1 */

					1 18  2  0  1  0 	/* RxD2 */

					1 19  2  0  1  0 	/* RxD3 */

					1 1a  2  0  1  0 	/* RX_ER */

					1 1b  1  0  1  0 	/* TX_ER */

					1 1c  2  0  1  0 	/* RX_DV */

					1 1d  2  0  1  0 	/* COL */

					1 1e  1  0  1  0 	/* TX_EN */

					1 1f  2  0  1  0>;/* CRS */

					1 18  1  0  1  0 	/* TxD0 */

					1 19  1  0  1  0 	/* TxD1 */

					1 20  1  0  1  0 	/* TxD2 */

					1 21  1  0  1  0 	/* TxD3 */

					1 22  2  0  1  0 	/* RxD0 */

					1 23  2  0  1  0 	/* RxD1 */

					1 24  2  0  1  0 	/* RxD2 */

					1 25  2  0  1  0 	/* RxD3 */

					1 26  2  0  1  0 	/* RX_ER */

					1 27  1  0  1  0 	/* TX_ER */

					1 28  2  0  1  0 	/* RX_DV */

					1 29  2  0  1  0 	/* COL */

					1 30  1  0  1  0 	/* TX_EN */

					1 31  2  0  1  0>;	/* CRS */

			};

			pio5: ucc_pin@05 {

				pio-map = <
@@ -190,10 +192,10 @@ 
					2    0    1      0    2    0  /* TxD5 */

					2    8    2      0    2    0  /* RxD5 */



					2   1d    2      0    0    0  /* CTS5 */

					2   1f    1      0    2    0  /* RTS5 */

					2   29    2      0    0    0  /* CTS5 */

					2   31    1      0    2    0  /* RTS5 */



					2   18    2      0    0    0  /* CD */

					2   24    2      0    0    0  /* CD */



				>;

			};
@@ -206,28 +208,28 @@ 
		#size-cells = <1>;

		device_type = "qe";

		compatible = "fsl,qe";

		ranges = <0 e0100000 00100000>;

		reg = <e0100000 480>;

		ranges = <0x0 0xe0100000 0x00100000>;

		reg = <0xe0100000 0x480>;

		brg-frequency = <0>;

		bus-frequency = <BCD3D80>;

		bus-frequency = <198000000>;



		muram@10000 {

			#address-cells = <1>;

			#size-cells = <1>;

			compatible = "fsl,qe-muram", "fsl,cpm-muram";

			ranges = <0 00010000 00004000>;

			ranges = <0x0 0x00010000 0x00004000>;



			data-only@0 {

				compatible = "fsl,qe-muram-data",

					     "fsl,cpm-muram-data";

				reg = <0 4000>;

				reg = <0x0 0x4000>;

			};

		};



		spi@4c0 {

			cell-index = <0>;

			compatible = "fsl,spi";

			reg = <4c0 40>;

			reg = <0x4c0 0x40>;

			interrupts = <2>;

			interrupt-parent = <&qeic>;

			mode = "cpu";
@@ -236,7 +238,7 @@ 
		spi@500 {

			cell-index = <1>;

			compatible = "fsl,spi";

			reg = <500 40>;

			reg = <0x500 0x40>;

			interrupts = <1>;

			interrupt-parent = <&qeic>;

			mode = "cpu";
@@ -244,8 +246,8 @@ 


		usb@6c0 {

			compatible = "qe_udc";

			reg = <6c0 40 8B00 100>;

			interrupts = <b>;

			reg = <0x6c0 0x40 0x8b00 0x100>;

			interrupts = <11>;

			interrupt-parent = <&qeic>;

			mode = "slave";

		};
@@ -256,8 +258,8 @@ 
			model = "UCC";

			cell-index = <3>;

			device-id = <3>;

			reg = <2200 200>;

			interrupts = <22>;

			reg = <0x2200 0x200>;

			interrupts = <34>;

			interrupt-parent = <&qeic>;

			local-mac-address = [ 00 00 00 00 00 00 ];

			rx-clock-name = "clk9";
@@ -272,8 +274,8 @@ 
			model = "UCC";

			cell-index = <4>;

			device-id = <4>;

			reg = <3200 200>;

			interrupts = <23>;

			reg = <0x3200 0x200>;

			interrupts = <35>;

			interrupt-parent = <&qeic>;

			local-mac-address = [ 00 00 00 00 00 00 ];

			rx-clock-name = "clk7";
@@ -289,8 +291,8 @@ 
			device-id = <5>;	/* The UCC number, 1-7*/

			port-number = <0>;	/* Which ttyQEx device */

			soft-uart;		/* We need Soft-UART */

			reg = <2400 200>;

			interrupts = <28>;	/* From Table 18-12 */

			reg = <0x2400 0x200>;

			interrupts = <40>;	/* From Table 18-12 */

			interrupt-parent = < &qeic >;

			/*

			 * For Soft-UART, we need to set TX to 1X, which
@@ -305,19 +307,19 @@ 
		mdio@2320 {

			#address-cells = <1>;

			#size-cells = <0>;

			reg = <2320 18>;

			reg = <0x2320 0x18>;

			compatible = "fsl,ucc-mdio";



			phy3: ethernet-phy@03 {

				interrupt-parent = <&ipic>;

				interrupts = <11 8>;

				reg = <3>;

				interrupts = <17 0x8>;

				reg = <0x3>;

				device_type = "ethernet-phy";

			};

			phy4: ethernet-phy@04 {

				interrupt-parent = <&ipic>;

				interrupts = <12 8>;

				reg = <4>;

				interrupts = <18 0x8>;

				reg = <0x4>;

				device_type = "ethernet-phy";

			};

		};
@@ -327,69 +329,69 @@ 
			compatible = "fsl,qe-ic";

			#address-cells = <0>;

			#interrupt-cells = <1>;

			reg = <80 80>;

			reg = <0x80 0x80>;

			big-endian;

			interrupts = <20 8 21 8>; //high:32 low:33

			interrupts = <32 0x8 33 0x8>; //high:32 low:33

			interrupt-parent = <&ipic>;

		};

	};



	pci0: pci@e0008500 {

		cell-index = <1>;

		interrupt-map-mask = <f800 0 0 7>;

		interrupt-map-mask = <0xf800 0x0 0x0 0x7>;

		interrupt-map = <

				/* IDSEL 0x11 AD17 */

				 8800 0 0 1 &ipic 14 8

				 8800 0 0 2 &ipic 15 8

				 8800 0 0 3 &ipic 16 8

				 8800 0 0 4 &ipic 17 8

				 0x8800 0x0 0x0 0x1 &ipic 20 0x8

				 0x8800 0x0 0x0 0x2 &ipic 21 0x8

				 0x8800 0x0 0x0 0x3 &ipic 22 0x8

				 0x8800 0x0 0x0 0x4 &ipic 23 0x8



				/* IDSEL 0x12 AD18 */

				 9000 0 0 1 &ipic 16 8

				 9000 0 0 2 &ipic 17 8

				 9000 0 0 3 &ipic 14 8

				 9000 0 0 4 &ipic 15 8

				 0x9000 0x0 0x0 0x1 &ipic 22 0x8

				 0x9000 0x0 0x0 0x2 &ipic 23 0x8

				 0x9000 0x0 0x0 0x3 &ipic 20 0x8

				 0x9000 0x0 0x0 0x4 &ipic 21 0x8



				/* IDSEL 0x13 AD19 */

				 9800 0 0 1 &ipic 17 8

				 9800 0 0 2 &ipic 14 8

				 9800 0 0 3 &ipic 15 8

				 9800 0 0 4 &ipic 16 8

				 0x9800 0x0 0x0 0x1 &ipic 23 0x8

				 0x9800 0x0 0x0 0x2 &ipic 20 0x8

				 0x9800 0x0 0x0 0x3 &ipic 21 0x8

				 0x9800 0x0 0x0 0x4 &ipic 22 0x8



				/* IDSEL 0x15 AD21*/

				 a800 0 0 1 &ipic 14 8

				 a800 0 0 2 &ipic 15 8

				 a800 0 0 3 &ipic 16 8

				 a800 0 0 4 &ipic 17 8

				 0xa800 0x0 0x0 0x1 &ipic 20 0x8

				 0xa800 0x0 0x0 0x2 &ipic 21 0x8

				 0xa800 0x0 0x0 0x3 &ipic 22 0x8

				 0xa800 0x0 0x0 0x4 &ipic 23 0x8



				/* IDSEL 0x16 AD22*/

				 b000 0 0 1 &ipic 17 8

				 b000 0 0 2 &ipic 14 8

				 b000 0 0 3 &ipic 15 8

				 b000 0 0 4 &ipic 16 8

				 0xb000 0x0 0x0 0x1 &ipic 23 0x8

				 0xb000 0x0 0x0 0x2 &ipic 20 0x8

				 0xb000 0x0 0x0 0x3 &ipic 21 0x8

				 0xb000 0x0 0x0 0x4 &ipic 22 0x8



				/* IDSEL 0x17 AD23*/

				 b800 0 0 1 &ipic 16 8

				 b800 0 0 2 &ipic 17 8

				 b800 0 0 3 &ipic 14 8

				 b800 0 0 4 &ipic 15 8

				 0xb800 0x0 0x0 0x1 &ipic 22 0x8

				 0xb800 0x0 0x0 0x2 &ipic 23 0x8

				 0xb800 0x0 0x0 0x3 &ipic 20 0x8

				 0xb800 0x0 0x0 0x4 &ipic 21 0x8



				/* IDSEL 0x18 AD24*/

				 c000 0 0 1 &ipic 15 8

				 c000 0 0 2 &ipic 16 8

				 c000 0 0 3 &ipic 17 8

				 c000 0 0 4 &ipic 14 8>;

				 0xc000 0x0 0x0 0x1 &ipic 21 0x8

				 0xc000 0x0 0x0 0x2 &ipic 22 0x8

				 0xc000 0x0 0x0 0x3 &ipic 23 0x8

				 0xc000 0x0 0x0 0x4 &ipic 20 0x8>;

		interrupt-parent = <&ipic>;

		interrupts = <42 8>;

		bus-range = <0 0>;

		ranges = <02000000 0 90000000 90000000 0 10000000

			  42000000 0 80000000 80000000 0 10000000

			  01000000 0 00000000 d0000000 0 00100000>;

		interrupts = <66 0x8>;

		bus-range = <0x0 0x0>;

		ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000

			  0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000

			  0x01000000 0x0 0x00000000 0xd0000000 0x0 0x00100000>;

		clock-frequency = <0>;

		#interrupt-cells = <1>;

		#size-cells = <2>;

		#address-cells = <3>;

		reg = <e0008500 100>;

		reg = <0xe0008500 0x100>;

		compatible = "fsl,mpc8349-pci";

		device_type = "pci";

	};

arch/powerpc/boot/dts/mpc832x_rdb.dts

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arch/powerpc/boot/dts/mpc8349emitx.dts

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