drm/i915/rkl: Handle new DPCLKA_CFGCR0 layout (cd803bb4) · Commits · 戴 / test

drivers/gpu/drm/i915/display/intel_ddi.c

+15 −3

Original line number	Diff line number	Diff line
		@@ -2845,7 +2845,9 @@ hsw_set_signal_levels(struct intel_dp *intel_dp)
		static u32 icl_dpclka_cfgcr0_clk_off(struct drm_i915_private *dev_priv,
		enum phy phy)
		{
		if (intel_phy_is_combo(dev_priv, phy)) {
		if (IS_ROCKETLAKE(dev_priv)) {
		return RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
		} else if (intel_phy_is_combo(dev_priv, phy)) {
		return ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
		} else if (intel_phy_is_tc(dev_priv, phy)) {
		enum tc_port tc_port = intel_port_to_tc(dev_priv,
		@@ -2872,6 +2874,16 @@ static void icl_map_plls_to_ports(struct intel_encoder *encoder,
		(val & icl_dpclka_cfgcr0_clk_off(dev_priv, phy)) == 0);

		if (intel_phy_is_combo(dev_priv, phy)) {
		u32 mask, sel;

		if (IS_ROCKETLAKE(dev_priv)) {
		mask = RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
		sel = RKL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy);
		} else {
		mask = ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
		sel = ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy);
		}

		/*
		* Even though this register references DDIs, note that we
		* want to pass the PHY rather than the port (DDI). For
		@@ -2882,8 +2894,8 @@ static void icl_map_plls_to_ports(struct intel_encoder *encoder,
		* Clock Select chooses the PLL for both DDIA and DDID and
		* drives port A in all cases."
		*/
		val &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
		val \|= ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy);
		val &= ~mask;
		val \|= sel;
		intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val);
		intel_de_posting_read(dev_priv, ICL_DPCLKA_CFGCR0);
		}

+12 −3

Original line number	Diff line number	Diff line
		@@ -10802,9 +10802,18 @@ static void icl_get_ddi_pll(struct drm_i915_private *dev_priv, enum port port,
		u32 temp;

		if (intel_phy_is_combo(dev_priv, phy)) {
		temp = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0) &
		ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
		id = temp >> ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy);
		u32 mask, shift;

		if (IS_ROCKETLAKE(dev_priv)) {
		mask = RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
		shift = RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy);
		} else {
		mask = ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
		shift = ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy);
		}

		temp = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0) & mask;
		id = temp >> shift;
		port_dpll_id = ICL_PORT_DPLL_DEFAULT;
		} else if (intel_phy_is_tc(dev_priv, phy)) {
		u32 clk_sel = intel_de_read(dev_priv, DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK;

+6 −0

Original line number	Diff line number	Diff line
		@@ -10279,12 +10279,18 @@ enum skl_power_gate {

		#define ICL_DPCLKA_CFGCR0 _MMIO(0x164280)
		#define ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy) (1 << _PICK(phy, 10, 11, 24))
		#define RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy) REG_BIT((phy) + 10)
		#define ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port) (1 << ((tc_port) < PORT_TC4 ? \
		(tc_port) + 12 : \
		(tc_port) - PORT_TC4 + 21))
		#define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy) ((phy) * 2)
		#define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy) (3 << ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
		#define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll, phy) ((pll) << ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
		#define RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy) _PICK(phy, 0, 2, 4, 27)
		#define RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy) \
		(3 << RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
		#define RKL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll, phy) \
		((pll) << RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))

		/* CNL PLL */
		#define DPLL0_ENABLE 0x46010