Commit cd7879f7 authored by Xiong Zhang's avatar Xiong Zhang Committed by Zhenyu Wang
Browse files

drm/i915/gvt: Roundup fb->height into tile's height at calucation fb->size 



When fb is tiled and fb->height isn't the multiple of tile's height,
the format fb->size = fb->stride * fb->height, will get a smaller size
than the actual size. As the memory height of tiled fb should be multiple
of tile's height.

Fixes: 7f1a93b1 ("drm/i915/gvt: Correct the calculation of plane size")
Reviewed-by: default avatarZhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: default avatarXiong Zhang <xiong.y.zhang@intel.com>
Signed-off-by: default avatarZhenyu Wang <zhenyuw@linux.intel.com>
parent 968a85b1

drivers/gpu/drm/i915/gvt/dmabuf.c

+6 −3
Original line number Diff line number Diff line
@@ -209,7 +209,7 @@ static int vgpu_get_plane_info(struct drm_device *dev, 
	struct drm_i915_private *dev_priv = to_i915(dev);

	struct intel_vgpu_primary_plane_format p;

	struct intel_vgpu_cursor_plane_format c;

	int ret;

	int ret, tile_height = 1;



	if (plane_id == DRM_PLANE_TYPE_PRIMARY) {

		ret = intel_vgpu_decode_primary_plane(vgpu, &p);
@@ -228,12 +228,15 @@ static int vgpu_get_plane_info(struct drm_device *dev, 
			break;

		case PLANE_CTL_TILED_X:

			info->drm_format_mod = I915_FORMAT_MOD_X_TILED;

			tile_height = 8;

			break;

		case PLANE_CTL_TILED_Y:

			info->drm_format_mod = I915_FORMAT_MOD_Y_TILED;

			tile_height = 32;

			break;

		case PLANE_CTL_TILED_YF:

			info->drm_format_mod = I915_FORMAT_MOD_Yf_TILED;

			tile_height = 32;

			break;

		default:

			gvt_vgpu_err("invalid tiling mode: %x\n", p.tiled);
@@ -264,8 +267,8 @@ static int vgpu_get_plane_info(struct drm_device *dev, 
		return -EINVAL;

	}



	info->size = (info->stride * info->height + PAGE_SIZE - 1)

		      >> PAGE_SHIFT;

	info->size = (info->stride * roundup(info->height, tile_height)

		      + PAGE_SIZE - 1) >> PAGE_SHIFT;

	if (info->size == 0) {

		gvt_vgpu_err("fb size is zero\n");

		return -EINVAL;

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