arch/tile: support <asm/cachectl.h> header for cacheflush() syscall

header-y += ../arch/

header-y += cachectl.h

header-y += ucontext.h

header-y += hardwall.h

/*

 * Copyright 2011 Tilera Corporation. All Rights Reserved.

 *

 *   This program is free software; you can redistribute it and/or

 *   modify it under the terms of the GNU General Public License

 *   as published by the Free Software Foundation, version 2.

 *

 *   This program is distributed in the hope that it will be useful, but

 *   WITHOUT ANY WARRANTY; without even the implied warranty of

 *   MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or

 *   NON INFRINGEMENT.  See the GNU General Public License for

 *   more details.

 */

#ifndef _ASM_TILE_CACHECTL_H

#define _ASM_TILE_CACHECTL_H

/*

 * Options for cacheflush system call.

 *

 * The ICACHE flush is performed on all cores currently running the

 * current process's address space.  The intent is for user

 * applications to be able to modify code, invoke the system call,

 * then allow arbitrary other threads in the same address space to see

 * the newly-modified code.  Passing a length of CHIP_L1I_CACHE_SIZE()

 * or more invalidates the entire icache on all cores in the address

 * spaces.  (Note: currently this option invalidates the entire icache

 * regardless of the requested address and length, but we may choose

 * to honor the arguments at some point.)

 *

 * Flush and invalidation of memory can normally be performed with the

 * __insn_flush(), __insn_inv(), and __insn_finv() instructions from

 * userspace.  The DCACHE option to the system call allows userspace

 * to flush the entire L1+L2 data cache from the core.  In this case,

 * the address and length arguments are not used.  The DCACHE flush is

 * restricted to the current core, not all cores in the address space.

 */

#define	ICACHE	(1<<0)		/* invalidate L1 instruction cache */

#define	DCACHE	(1<<1)		/* flush and invalidate data cache */

#define	BCACHE	(ICACHE|DCACHE)	/* flush both caches               */

#endif	/* _ASM_TILE_CACHECTL_H */

long compat_sys_sched_rr_get_interval(compat_pid_t pid,

				      struct compat_timespec __user *interval);

/* Tilera Linux syscalls that don't have "compat" versions. */

#define compat_sys_flush_cache sys_flush_cache

/* These are the intvec_64.S trampolines. */

long _compat_sys_execve(const char __user *path,

			const compat_uptr_t __user *argv,

		     u32 len, int advice);

int sys32_fadvise64_64(int fd, u32 offset_lo, u32 offset_hi,

		       u32 len_lo, u32 len_hi, int advice);

long sys_flush_cache(void);

long sys_cacheflush(unsigned long addr, unsigned long len,

		    unsigned long flags);

#ifndef __tilegx__  /* No mmap() in the 32-bit kernel. */

#define sys_mmap sys_mmap

#endif

#include <asm-generic/unistd.h>

/* Additional Tilera-specific syscalls. */

#define __NR_flush_cache	(__NR_arch_specific_syscall + 1)

__SYSCALL(__NR_flush_cache, sys_flush_cache)

#define __NR_cacheflush	(__NR_arch_specific_syscall + 1)

__SYSCALL(__NR_cacheflush, sys_cacheflush)

#ifndef __tilegx__

/* "Fast" syscalls provide atomic support for 32-bit chips. */