Commit cd50065b authored by Takashi Iwai's avatar Takashi Iwai
Browse files

ALSA: hda - Revert stream assignment order for Intel controllers 



We got a regression report for 3.15.x kernels, and this turned out to
be triggered by the fix for stream assignment order.  On reporter's
machine with Intel controller (8086:1e20) + VIA VT1802 codec, the
first playback slot can't work with speaker outputs.

But the original commit was actually a fix for AMD controllers where
no proper GCAP value is returned, we shouldn't revert the whole
commit.  Instead, in this patch, a new flag is introduced to determine
the stream assignment order, and follow the old behavior for Intel
controllers.

Fixes: dcb32ecd ('ALSA: hda - Do not assign streams in reverse order')
Reported-and-tested-by: default avatarSteven Newbury <steve@snewbury.org.uk>
Cc: <stable@vger.kernel.org> [v3.15+]
Signed-off-by: default avatarTakashi Iwai <tiwai@suse.de>
parent 91947d8c

sound/pci/hda/hda_controller.c

+2 −1
Original line number Diff line number Diff line
@@ -193,7 +193,8 @@ azx_assign_device(struct azx *chip, struct snd_pcm_substream *substream) 
				dsp_unlock(azx_dev);

				return azx_dev;

			}

			if (!res)

			if (!res ||

			    (chip->driver_caps & AZX_DCAPS_REVERSE_ASSIGN))

				res = azx_dev;

		}

		dsp_unlock(azx_dev);

sound/pci/hda/hda_intel.c

+1 −1
Original line number Diff line number Diff line
@@ -227,7 +227,7 @@ enum { 
/* quirks for Intel PCH */

#define AZX_DCAPS_INTEL_PCH_NOPM \

	(AZX_DCAPS_SCH_SNOOP | AZX_DCAPS_BUFSIZE | \

	 AZX_DCAPS_COUNT_LPIB_DELAY)

	 AZX_DCAPS_COUNT_LPIB_DELAY | AZX_DCAPS_REVERSE_ASSIGN)



#define AZX_DCAPS_INTEL_PCH \

	(AZX_DCAPS_INTEL_PCH_NOPM | AZX_DCAPS_PM_RUNTIME)

sound/pci/hda/hda_priv.h

+1 −0
Original line number Diff line number Diff line
@@ -186,6 +186,7 @@ enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 }; 
#define AZX_DCAPS_BUFSIZE	(1 << 21)	/* no buffer size alignment */

#define AZX_DCAPS_ALIGN_BUFSIZE	(1 << 22)	/* buffer size alignment */

#define AZX_DCAPS_4K_BDLE_BOUNDARY (1 << 23)	/* BDLE in 4k boundary */

#define AZX_DCAPS_REVERSE_ASSIGN (1 << 24)	/* Assign devices in reverse order */

#define AZX_DCAPS_COUNT_LPIB_DELAY  (1 << 25)	/* Take LPIB as delay */

#define AZX_DCAPS_PM_RUNTIME	(1 << 26)	/* runtime PM support */

#define AZX_DCAPS_I915_POWERWELL (1 << 27)	/* HSW i915 powerwell support */

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