drm/amdgpu/vcn2.5: wait for tiles off after unpause (cd4df4e6) · Commits · 戴 / test

drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c

+3 −3

Original line number	Diff line number	Diff line
		@@ -1404,7 +1404,7 @@ static int vcn_v2_5_pause_dpg_mode(struct amdgpu_device *adev,
		{
		struct amdgpu_ring *ring;
		uint32_t reg_data = 0;
		int ret_code;
		int ret_code = 0;

		/* pause/unpause if state is changed */
		if (adev->vcn.inst[inst_idx].pause_state.fw_based != new_state->fw_based) {
		@@ -1414,7 +1414,6 @@ static int vcn_v2_5_pause_dpg_mode(struct amdgpu_device *adev,
		(~UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK);

		if (new_state->fw_based == VCN_DPG_STATE__PAUSE) {
		ret_code = 0;
		SOC15_WAIT_ON_RREG(UVD, inst_idx, mmUVD_POWER_STATUS, 0x1,
		UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, ret_code);

		@@ -1469,9 +1468,10 @@ static int vcn_v2_5_pause_dpg_mode(struct amdgpu_device *adev,
		UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON, UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, ret_code);
		}
		} else {
		/* unpause dpg, no need to wait */
		reg_data &= ~UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK;
		WREG32_SOC15(UVD, inst_idx, mmUVD_DPG_PAUSE, reg_data);
		SOC15_WAIT_ON_RREG(UVD, inst_idx, mmUVD_POWER_STATUS, 0x1,
		UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, ret_code);
		}
		adev->vcn.inst[inst_idx].pause_state.fw_based = new_state->fw_based;
		}