Commit cd4d6f35 authored by Joseph Lo's avatar Joseph Lo Committed by Thierry Reding
Browse files

clk: tegra: Add PLLP_UD and PLLMB_UD for Tegra210 



Introduce the low jitter path of PLLP and PLLMB which can be used as EMC
clock source.

Signed-off-by: default avatarJoseph Lo <josephl@nvidia.com>
Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
parent 3dcbd36f

drivers/clk/tegra/clk-tegra210.c

+11 −0
Original line number Diff line number Diff line
@@ -3153,6 +3153,17 @@ static void __init tegra210_pll_init(void __iomem *clk_base, 
	clk_register_clkdev(clk, "pll_m_ud", NULL);

	clks[TEGRA210_CLK_PLL_M_UD] = clk;



	/* PLLMB_UD */

	clk = clk_register_fixed_factor(NULL, "pll_mb_ud", "pll_mb",

					CLK_SET_RATE_PARENT, 1, 1);

	clk_register_clkdev(clk, "pll_mb_ud", NULL);

	clks[TEGRA210_CLK_PLL_MB_UD] = clk;



	/* PLLP_UD */

	clk = clk_register_fixed_factor(NULL, "pll_p_ud", "pll_p",

					0, 1, 1);

	clks[TEGRA210_CLK_PLL_P_UD] = clk;



	/* PLLU_VCO */

	if (!tegra210_init_pllu()) {

		clk = clk_register_fixed_rate(NULL, "pll_u_vco", "pll_ref", 0,

include/dt-bindings/clock/tegra210-car.h

+2 −2
Original line number Diff line number Diff line
@@ -351,8 +351,8 @@ 
#define TEGRA210_CLK_PLL_P_OUT_XUSB 317

#define TEGRA210_CLK_XUSB_SSP_SRC 318

#define TEGRA210_CLK_PLL_RE_OUT1 319

/* 320 */

/* 321 */

#define TEGRA210_CLK_PLL_MB_UD 320

#define TEGRA210_CLK_PLL_P_UD 321

#define TEGRA210_CLK_ISP 322

#define TEGRA210_CLK_PLL_A_OUT_ADSP 323

#define TEGRA210_CLK_PLL_A_OUT0_OUT_ADSP 324

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