Commit cd248341 authored by Jan Glauber's avatar Jan Glauber Committed by Martin Schwidefsky
Browse files

s390/pci: base support 



Add PCI support for s390, (only 64 bit mode is supported by hardware):
- PCI facility tests
- PCI instructions: pcilg, pcistg, pcistb, stpcifc, mpcifc, rpcit
- map readb/w/l/q and writeb/w/l/q to pcilg and pcistg instructions
- pci_iomap implementation
- memcpy_fromio/toio
- pci_root_ops using special pcilg/pcistg
- device, bus and domain allocation

Signed-off-by: default avatarJan Glauber <jang@linux.vnet.ibm.com>
Signed-off-by: default avatarMartin Schwidefsky <schwidefsky@de.ibm.com>
parent d07dc5d8

arch/s390/Kbuild

+1 −0
Original line number Diff line number Diff line
@@ -6,3 +6,4 @@ obj-$(CONFIG_S390_HYPFS_FS) += hypfs/ 
obj-$(CONFIG_APPLDATA_BASE)	+= appldata/

obj-$(CONFIG_MATHEMU)		+= math-emu/

obj-y				+= net/

obj-$(CONFIG_PCI)		+= pci/

arch/s390/include/asm/io.h

+51 −4
Original line number Diff line number Diff line
@@ -9,9 +9,9 @@ 
#ifndef _S390_IO_H

#define _S390_IO_H



#include <linux/kernel.h>

#include <asm/page.h>



#define IO_SPACE_LIMIT 0xffffffff

#include <asm/pci_io.h>



/*

 * Change virtual addresses to physical addresses and vv.
@@ -28,6 +28,7 @@ static inline unsigned long virt_to_phys(volatile void * address) 
		 : "=a" (real_address) : "a" (address) : "cc");

	return real_address;

}

#define virt_to_phys virt_to_phys



static inline void * phys_to_virt(unsigned long address)

{
@@ -42,4 +43,50 @@ void unxlate_dev_mem_ptr(unsigned long phys, void *addr); 
 */

#define xlate_dev_kmem_ptr(p)	p



#define IO_SPACE_LIMIT 0



#ifdef CONFIG_PCI



#define ioremap_nocache(addr, size)	ioremap(addr, size)

#define ioremap_wc			ioremap_nocache



/* TODO: s390 cannot support io_remap_pfn_range... */

#define io_remap_pfn_range(vma, vaddr, pfn, size, prot) 	       \

	remap_pfn_range(vma, vaddr, pfn, size, prot)



static inline void __iomem *ioremap(unsigned long offset, unsigned long size)

{

	return (void __iomem *) offset;

}



static inline void iounmap(volatile void __iomem *addr)

{

}



/*

 * s390 needs a private implementation of pci_iomap since ioremap with its

 * offset parameter isn't sufficient. That's because BAR spaces are not

 * disjunctive on s390 so we need the bar parameter of pci_iomap to find

 * the corresponding device and create the mapping cookie.

 */

#define pci_iomap pci_iomap

#define pci_iounmap pci_iounmap



#define memcpy_fromio(dst, src, count)	zpci_memcpy_fromio(dst, src, count)

#define memcpy_toio(dst, src, count)	zpci_memcpy_toio(dst, src, count)

#define memset_io(dst, val, count)	zpci_memset_io(dst, val, count)



#define __raw_readb	zpci_read_u8

#define __raw_readw	zpci_read_u16

#define __raw_readl	zpci_read_u32

#define __raw_readq	zpci_read_u64

#define __raw_writeb	zpci_write_u8

#define __raw_writew	zpci_write_u16

#define __raw_writel	zpci_write_u32

#define __raw_writeq	zpci_write_u64



#endif /* CONFIG_PCI */



#include <asm-generic/io.h>



#endif

arch/s390/include/asm/pci.h

+78 −4
Original line number Diff line number Diff line 
#ifndef __ASM_S390_PCI_H

#define __ASM_S390_PCI_H



/* S/390 systems don't have a PCI bus. This file is just here because some stupid .c code

 * includes it even if CONFIG_PCI is not set.

 */

/* must be set before including asm-generic/pci.h */

#define PCI_DMA_BUS_IS_PHYS (0)

/* must be set before including pci_clp.h */

#define PCI_BAR_COUNT	6



#endif /* __ASM_S390_PCI_H */

#include <asm-generic/pci.h>

#include <asm-generic/pci-dma-compat.h>



#define PCIBIOS_MIN_IO		0x1000

#define PCIBIOS_MIN_MEM		0x10000000



#define pcibios_assign_all_busses()	(0)



void __iomem *pci_iomap(struct pci_dev *, int, unsigned long);

void pci_iounmap(struct pci_dev *, void __iomem *);

int pci_domain_nr(struct pci_bus *);

int pci_proc_domain(struct pci_bus *);



#define ZPCI_BUS_NR			0	/* default bus number */

#define ZPCI_DEVFN			0	/* default device number */



/* PCI Function Controls */

#define ZPCI_FC_FN_ENABLED		0x80

#define ZPCI_FC_ERROR			0x40

#define ZPCI_FC_BLOCKED			0x20

#define ZPCI_FC_DMA_ENABLED		0x10



enum zpci_state {

	ZPCI_FN_STATE_RESERVED,

	ZPCI_FN_STATE_STANDBY,

	ZPCI_FN_STATE_CONFIGURED,

	ZPCI_FN_STATE_ONLINE,

	NR_ZPCI_FN_STATES,

};



struct zpci_bar_struct {

	u32		val;		/* bar start & 3 flag bits */

	u8		size;		/* order 2 exponent */

	u16		map_idx;	/* index into bar mapping array */

};



/* Private data per function */

struct zpci_dev {

	struct pci_dev	*pdev;

	struct pci_bus	*bus;

	struct list_head entry;		/* list of all zpci_devices, needed for hotplug, etc. */



	enum zpci_state state;

	u32		fid;		/* function ID, used by sclp */

	u32		fh;		/* function handle, used by insn's */

	u16		pchid;		/* physical channel ID */

	u8		pfgid;		/* function group ID */

	u16		domain;



	struct zpci_bar_struct bars[PCI_BAR_COUNT];



	enum pci_bus_speed max_bus_speed;

};



static inline bool zdev_enabled(struct zpci_dev *zdev)

{

	return (zdev->fh & (1UL << 31)) ? true : false;

}



/* -----------------------------------------------------------------------------

  Prototypes

----------------------------------------------------------------------------- */

/* Base stuff */

struct zpci_dev *zpci_alloc_device(void);

int zpci_create_device(struct zpci_dev *);

int zpci_enable_device(struct zpci_dev *);

void zpci_stop_device(struct zpci_dev *);

void zpci_free_device(struct zpci_dev *);

int zpci_scan_device(struct zpci_dev *);



/* Helpers */

struct zpci_dev *get_zdev(struct pci_dev *);

struct zpci_dev *get_zdev_by_fid(u32);

bool zpci_fid_present(u32);



#endif

arch/s390/include/asm/pci_insn.h

0 → 100644
+280 −0
Original line number Diff line number Diff line 
#ifndef _ASM_S390_PCI_INSN_H

#define _ASM_S390_PCI_INSN_H



#include <linux/delay.h>



#define ZPCI_INSN_BUSY_DELAY	1	/* 1 millisecond */



/* Load/Store status codes */

#define ZPCI_PCI_ST_FUNC_NOT_ENABLED		4

#define ZPCI_PCI_ST_FUNC_IN_ERR			8

#define ZPCI_PCI_ST_BLOCKED			12

#define ZPCI_PCI_ST_INSUF_RES			16

#define ZPCI_PCI_ST_INVAL_AS			20

#define ZPCI_PCI_ST_FUNC_ALREADY_ENABLED	24

#define ZPCI_PCI_ST_DMA_AS_NOT_ENABLED		28

#define ZPCI_PCI_ST_2ND_OP_IN_INV_AS		36

#define ZPCI_PCI_ST_FUNC_NOT_AVAIL		40

#define ZPCI_PCI_ST_ALREADY_IN_RQ_STATE		44



/* Load/Store return codes */

#define ZPCI_PCI_LS_OK				0

#define ZPCI_PCI_LS_ERR				1

#define ZPCI_PCI_LS_BUSY			2

#define ZPCI_PCI_LS_INVAL_HANDLE		3



/* Load/Store address space identifiers */

#define ZPCI_PCIAS_MEMIO_0			0

#define ZPCI_PCIAS_MEMIO_1			1

#define ZPCI_PCIAS_MEMIO_2			2

#define ZPCI_PCIAS_MEMIO_3			3

#define ZPCI_PCIAS_MEMIO_4			4

#define ZPCI_PCIAS_MEMIO_5			5

#define ZPCI_PCIAS_CFGSPC			15



/* Modify PCI Function Controls */

#define ZPCI_MOD_FC_REG_INT	2

#define ZPCI_MOD_FC_DEREG_INT	3

#define ZPCI_MOD_FC_REG_IOAT	4

#define ZPCI_MOD_FC_DEREG_IOAT	5

#define ZPCI_MOD_FC_REREG_IOAT	6

#define ZPCI_MOD_FC_RESET_ERROR	7

#define ZPCI_MOD_FC_RESET_BLOCK	9

#define ZPCI_MOD_FC_SET_MEASURE	10



/* FIB function controls */

#define ZPCI_FIB_FC_ENABLED	0x80

#define ZPCI_FIB_FC_ERROR	0x40

#define ZPCI_FIB_FC_LS_BLOCKED	0x20

#define ZPCI_FIB_FC_DMAAS_REG	0x10



/* FIB function controls */

#define ZPCI_FIB_FC_ENABLED	0x80

#define ZPCI_FIB_FC_ERROR	0x40

#define ZPCI_FIB_FC_LS_BLOCKED	0x20

#define ZPCI_FIB_FC_DMAAS_REG	0x10



/* Function Information Block */

struct zpci_fib {

	u32 fmt		:  8;	/* format */

	u32		: 24;

	u32 reserved1;

	u8 fc;			/* function controls */

	u8 reserved2;

	u16 reserved3;

	u32 reserved4;

	u64 pba;		/* PCI base address */

	u64 pal;		/* PCI address limit */

	u64 iota;		/* I/O Translation Anchor */

	u32		:  1;

	u32 isc		:  3;	/* Interrupt subclass */

	u32 noi		: 12;	/* Number of interrupts */

	u32		:  2;

	u32 aibvo	:  6;	/* Adapter interrupt bit vector offset */

	u32 sum		:  1;	/* Adapter int summary bit enabled */

	u32		:  1;

	u32 aisbo	:  6;	/* Adapter int summary bit offset */

	u32 reserved5;

	u64 aibv;		/* Adapter int bit vector address */

	u64 aisb;		/* Adapter int summary bit address */

	u64 fmb_addr;		/* Function measurement block address and key */

	u64 reserved6;

	u64 reserved7;

} __packed;



/* Modify PCI Function Controls */

static inline u8 __mpcifc(u64 req, struct zpci_fib *fib, u8 *status)

{

	u8 cc;



	asm volatile (

		"	.insn	rxy,0xe300000000d0,%[req],%[fib]\n"

		"	ipm	%[cc]\n"

		"	srl	%[cc],28\n"

		: [cc] "=d" (cc), [req] "+d" (req), [fib] "+Q" (*fib)

		: : "cc");

	*status = req >> 24 & 0xff;

	return cc;

}



static inline int mpcifc_instr(u64 req, struct zpci_fib *fib)

{

	u8 cc, status;



	do {

		cc = __mpcifc(req, fib, &status);

		if (cc == 2)

			msleep(ZPCI_INSN_BUSY_DELAY);

	} while (cc == 2);



	if (cc)

		printk_once(KERN_ERR "%s: error cc: %d  status: %d\n",

			     __func__, cc, status);

	return (cc) ? -EIO : 0;

}



/* Refresh PCI Translations */

static inline u8 __rpcit(u64 fn, u64 addr, u64 range, u8 *status)

{

	register u64 __addr asm("2") = addr;

	register u64 __range asm("3") = range;

	u8 cc;



	asm volatile (

		"	.insn	rre,0xb9d30000,%[fn],%[addr]\n"

		"	ipm	%[cc]\n"

		"	srl	%[cc],28\n"

		: [cc] "=d" (cc), [fn] "+d" (fn)

		: [addr] "d" (__addr), "d" (__range)

		: "cc");

	*status = fn >> 24 & 0xff;

	return cc;

}



static inline int rpcit_instr(u64 fn, u64 addr, u64 range)

{

	u8 cc, status;



	do {

		cc = __rpcit(fn, addr, range, &status);

		if (cc == 2)

			msleep(ZPCI_INSN_BUSY_DELAY);

	} while (cc == 2);



	if (cc)

		printk_once(KERN_ERR "%s: error cc: %d  status: %d  dma_addr: %Lx  size: %Lx\n",

			    __func__, cc, status, addr, range);

	return (cc) ? -EIO : 0;

}



/* Store PCI function controls */

static inline u8 __stpcifc(u32 handle, u8 space, struct zpci_fib *fib, u8 *status)

{

	u64 fn = (u64) handle << 32 | space << 16;

	u8 cc;



	asm volatile (

		"	.insn	rxy,0xe300000000d4,%[fn],%[fib]\n"

		"	ipm	%[cc]\n"

		"	srl	%[cc],28\n"

		: [cc] "=d" (cc), [fn] "+d" (fn), [fib] "=m" (*fib)

		: : "cc");

	*status = fn >> 24 & 0xff;

	return cc;

}



/* Set Interruption Controls */

static inline void sic_instr(u16 ctl, char *unused, u8 isc)

{

	asm volatile (

		"	.insn	rsy,0xeb00000000d1,%[ctl],%[isc],%[u]\n"

		: : [ctl] "d" (ctl), [isc] "d" (isc << 27), [u] "Q" (*unused));

}



/* PCI Load */

static inline u8 __pcilg(u64 *data, u64 req, u64 offset, u8 *status)

{

	register u64 __req asm("2") = req;

	register u64 __offset asm("3") = offset;

	u64 __data;

	u8 cc;



	asm volatile (

		"	.insn	rre,0xb9d20000,%[data],%[req]\n"

		"	ipm	%[cc]\n"

		"	srl	%[cc],28\n"

		: [cc] "=d" (cc), [data] "=d" (__data), [req] "+d" (__req)

		:  "d" (__offset)

		: "cc");

	*status = __req >> 24 & 0xff;

	*data = __data;

	return cc;

}



static inline int pcilg_instr(u64 *data, u64 req, u64 offset)

{

	u8 cc, status;



	do {

		cc = __pcilg(data, req, offset, &status);

		if (cc == 2)

			msleep(ZPCI_INSN_BUSY_DELAY);

	} while (cc == 2);



	if (cc) {

		printk_once(KERN_ERR "%s: error cc: %d  status: %d  req: %Lx  offset: %Lx\n",

			    __func__, cc, status, req, offset);

		/* TODO: on IO errors set data to 0xff...

		 * here or in users of pcilg (le conversion)?

		 */

	}

	return (cc) ? -EIO : 0;

}



/* PCI Store */

static inline u8 __pcistg(u64 data, u64 req, u64 offset, u8 *status)

{

	register u64 __req asm("2") = req;

	register u64 __offset asm("3") = offset;

	u8 cc;



	asm volatile (

		"	.insn	rre,0xb9d00000,%[data],%[req]\n"

		"	ipm	%[cc]\n"

		"	srl	%[cc],28\n"

		: [cc] "=d" (cc), [req] "+d" (__req)

		: "d" (__offset), [data] "d" (data)

		: "cc");

	*status = __req >> 24 & 0xff;

	return cc;

}



static inline int pcistg_instr(u64 data, u64 req, u64 offset)

{

	u8 cc, status;



	do {

		cc = __pcistg(data, req, offset, &status);

		if (cc == 2)

			msleep(ZPCI_INSN_BUSY_DELAY);

	} while (cc == 2);



	if (cc)

		printk_once(KERN_ERR "%s: error cc: %d  status: %d  req: %Lx  offset: %Lx\n",

			__func__, cc, status, req, offset);

	return (cc) ? -EIO : 0;

}



/* PCI Store Block */

static inline u8 __pcistb(const u64 *data, u64 req, u64 offset, u8 *status)

{

	u8 cc;



	asm volatile (

		"	.insn	rsy,0xeb00000000d0,%[req],%[offset],%[data]\n"

		"	ipm	%[cc]\n"

		"	srl	%[cc],28\n"

		: [cc] "=d" (cc), [req] "+d" (req)

		: [offset] "d" (offset), [data] "Q" (*data)

		: "cc");

	*status = req >> 24 & 0xff;

	return cc;

}



static inline int pcistb_instr(const u64 *data, u64 req, u64 offset)

{

	u8 cc, status;



	do {

		cc = __pcistb(data, req, offset, &status);

		if (cc == 2)

			msleep(ZPCI_INSN_BUSY_DELAY);

	} while (cc == 2);



	if (cc)

		printk_once(KERN_ERR "%s: error cc: %d  status: %d  req: %Lx  offset: %Lx\n",

			    __func__, cc, status, req, offset);

	return (cc) ? -EIO : 0;

}



#endif

arch/s390/include/asm/pci_io.h

0 → 100644
+194 −0
Original line number Diff line number Diff line 
#ifndef _ASM_S390_PCI_IO_H

#define _ASM_S390_PCI_IO_H



#ifdef CONFIG_PCI



#include <linux/kernel.h>

#include <linux/slab.h>

#include <asm/pci_insn.h>



/* I/O Map */

#define ZPCI_IOMAP_MAX_ENTRIES		0x7fff

#define ZPCI_IOMAP_ADDR_BASE		0x8000000000000000ULL

#define ZPCI_IOMAP_ADDR_IDX_MASK	0x7fff000000000000ULL

#define ZPCI_IOMAP_ADDR_OFF_MASK	0x0000ffffffffffffULL



struct zpci_iomap_entry {

	u32 fh;

	u8 bar;

};



extern struct zpci_iomap_entry *zpci_iomap_start;



#define ZPCI_IDX(addr)								\

	(((__force u64) addr & ZPCI_IOMAP_ADDR_IDX_MASK) >> 48)

#define ZPCI_OFFSET(addr)							\

	((__force u64) addr & ZPCI_IOMAP_ADDR_OFF_MASK)



#define ZPCI_CREATE_REQ(handle, space, len)					\

	((u64) handle << 32 | space << 16 | len)



#define zpci_read(LENGTH, RETTYPE)						\

static inline RETTYPE zpci_read_##RETTYPE(const volatile void __iomem *addr)	\

{										\

	struct zpci_iomap_entry *entry = &zpci_iomap_start[ZPCI_IDX(addr)];	\

	u64 req = ZPCI_CREATE_REQ(entry->fh, entry->bar, LENGTH);		\

	u64 data;								\

	int rc;									\

										\

	rc = pcilg_instr(&data, req, ZPCI_OFFSET(addr));			\

	if (rc)									\

		data = -1ULL;							\

	return (RETTYPE) data;							\

}



#define zpci_write(LENGTH, VALTYPE)						\

static inline void zpci_write_##VALTYPE(VALTYPE val,				\

					const volatile void __iomem *addr)	\

{										\

	struct zpci_iomap_entry *entry = &zpci_iomap_start[ZPCI_IDX(addr)];	\

	u64 req = ZPCI_CREATE_REQ(entry->fh, entry->bar, LENGTH);		\

	u64 data = (VALTYPE) val;						\

										\

	pcistg_instr(data, req, ZPCI_OFFSET(addr));				\

}



zpci_read(8, u64)

zpci_read(4, u32)

zpci_read(2, u16)

zpci_read(1, u8)

zpci_write(8, u64)

zpci_write(4, u32)

zpci_write(2, u16)

zpci_write(1, u8)



static inline int zpci_write_single(u64 req, const u64 *data, u64 offset, u8 len)

{

	u64 val;



	switch (len) {

	case 1:

		val = (u64) *((u8 *) data);

		break;

	case 2:

		val = (u64) *((u16 *) data);

		break;

	case 4:

		val = (u64) *((u32 *) data);

		break;

	case 8:

		val = (u64) *((u64 *) data);

		break;

	default:

		val = 0;		/* let FW report error */

		break;

	}

	return pcistg_instr(val, req, offset);

}



static inline int zpci_read_single(u64 req, u64 *dst, u64 offset, u8 len)

{

	u64 data;

	u8 cc;



	cc = pcilg_instr(&data,	 req, offset);

	switch (len) {

	case 1:

		*((u8 *) dst) = (u8) data;

		break;

	case 2:

		*((u16 *) dst) = (u16) data;

		break;

	case 4:

		*((u32 *) dst) = (u32) data;

		break;

	case 8:

		*((u64 *) dst) = (u64) data;

		break;

	}

	return cc;

}



static inline int zpci_write_block(u64 req, const u64 *data, u64 offset)

{

	return pcistb_instr(data, req, offset);

}



static inline u8 zpci_get_max_write_size(u64 src, u64 dst, int len, int max)

{

	int count = len > max ? max : len, size = 1;



	while (!(src & 0x1) && !(dst & 0x1) && ((size << 1) <= count)) {

		dst = dst >> 1;

		src = src >> 1;

		size = size << 1;

	}

	return size;

}



static inline int zpci_memcpy_fromio(void *dst,

				     const volatile void __iomem *src,

				     unsigned long n)

{

	struct zpci_iomap_entry *entry = &zpci_iomap_start[ZPCI_IDX(src)];

	u64 req, offset = ZPCI_OFFSET(src);

	int size, rc = 0;



	while (n > 0) {

		size = zpci_get_max_write_size((u64) src, (u64) dst, n, 8);

		req = ZPCI_CREATE_REQ(entry->fh, entry->bar, size);

		rc = zpci_read_single(req, dst, offset, size);

		if (rc)

			break;

		offset += size;

		dst += size;

		n -= size;

	}

	return rc;

}



static inline int zpci_memcpy_toio(volatile void __iomem *dst,

				   const void *src, unsigned long n)

{

	struct zpci_iomap_entry *entry = &zpci_iomap_start[ZPCI_IDX(dst)];

	u64 req, offset = ZPCI_OFFSET(dst);

	int size, rc = 0;



	if (!src)

		return -EINVAL;



	while (n > 0) {

		size = zpci_get_max_write_size((u64) dst, (u64) src, n, 128);

		req = ZPCI_CREATE_REQ(entry->fh, entry->bar, size);



		if (size > 8) /* main path */

			rc = zpci_write_block(req, src, offset);

		else

			rc = zpci_write_single(req, src, offset, size);

		if (rc)

			break;

		offset += size;

		src += size;

		n -= size;

	}

	return rc;

}



static inline int zpci_memset_io(volatile void __iomem *dst,

				 unsigned char val, size_t count)

{

	u8 *src = kmalloc(count, GFP_KERNEL);

	int rc;



	if (src == NULL)

		return -ENOMEM;

	memset(src, val, count);



	rc = zpci_memcpy_toio(dst, src, count);

	kfree(src);

	return rc;

}



#endif /* CONFIG_PCI */



#endif /* _ASM_S390_PCI_IO_H */

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