Commit cce8ccca authored by Mauro Carvalho Chehab's avatar Mauro Carvalho Chehab
Browse files

media: use the BIT() macro 



As warned by cppcheck:

	[drivers/media/dvb-frontends/cx24123.c:434]: (error) Shifting signed 32-bit value by 31 bits is undefined behaviour
	[drivers/media/pci/bt8xx/bttv-input.c:87]: (error) Shifting signed 32-bit value by 31 bits is undefined behaviour
	[drivers/media/pci/bt8xx/bttv-input.c:98]: (error) Shifting signed 32-bit value by 31 bits is undefined behaviour
			...
	[drivers/media/v4l2-core/v4l2-ioctl.c:1391]: (error) Shifting signed 32-bit value by 31 bits is undefined behaviour

There are lots of places where we're doing 1 << 31. That's bad,
as, depending on the architecture, this has an undefined behavior.

The BIT() macro is already prepared to handle this, so, let's
just switch all "1 << number" macros by BIT(number) at the header files
with has 1 << 31.

Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> # exynos4-is and s3c-camif
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> # omap3isp, vsp1, xilinx, wl128x and ipu3
Reviewed-by: Benoit Parrot <bparrot@ti.com> # am437x and ti-vpe
Signed-off-by: default avatarMauro Carvalho Chehab <mchehab+samsung@kernel.org>
parent 093347ab

drivers/media/pci/cobalt/cobalt-driver.h

+32 −31
Original line number Diff line number Diff line
@@ -11,6 +11,7 @@ 
#ifndef COBALT_DRIVER_H

#define COBALT_DRIVER_H



#include <linux/bitops.h>

#include <linux/module.h>

#include <linux/pci.h>

#include <linux/spinlock.h>
@@ -61,37 +62,37 @@ 
#define COBALT_CLK		50000000



/* System status register */

#define COBALT_SYSSTAT_DIP0_MSK			(1 << 0)

#define COBALT_SYSSTAT_DIP1_MSK			(1 << 1)

#define COBALT_SYSSTAT_HSMA_PRSNTN_MSK		(1 << 2)

#define COBALT_SYSSTAT_FLASH_RDYBSYN_MSK	(1 << 3)

#define COBALT_SYSSTAT_VI0_5V_MSK		(1 << 4)

#define COBALT_SYSSTAT_VI0_INT1_MSK		(1 << 5)

#define COBALT_SYSSTAT_VI0_INT2_MSK		(1 << 6)

#define COBALT_SYSSTAT_VI0_LOST_DATA_MSK	(1 << 7)

#define COBALT_SYSSTAT_VI1_5V_MSK		(1 << 8)

#define COBALT_SYSSTAT_VI1_INT1_MSK		(1 << 9)

#define COBALT_SYSSTAT_VI1_INT2_MSK		(1 << 10)

#define COBALT_SYSSTAT_VI1_LOST_DATA_MSK	(1 << 11)

#define COBALT_SYSSTAT_VI2_5V_MSK		(1 << 12)

#define COBALT_SYSSTAT_VI2_INT1_MSK		(1 << 13)

#define COBALT_SYSSTAT_VI2_INT2_MSK		(1 << 14)

#define COBALT_SYSSTAT_VI2_LOST_DATA_MSK	(1 << 15)

#define COBALT_SYSSTAT_VI3_5V_MSK		(1 << 16)

#define COBALT_SYSSTAT_VI3_INT1_MSK		(1 << 17)

#define COBALT_SYSSTAT_VI3_INT2_MSK		(1 << 18)

#define COBALT_SYSSTAT_VI3_LOST_DATA_MSK	(1 << 19)

#define COBALT_SYSSTAT_VIHSMA_5V_MSK		(1 << 20)

#define COBALT_SYSSTAT_VIHSMA_INT1_MSK		(1 << 21)

#define COBALT_SYSSTAT_VIHSMA_INT2_MSK		(1 << 22)

#define COBALT_SYSSTAT_VIHSMA_LOST_DATA_MSK	(1 << 23)

#define COBALT_SYSSTAT_VOHSMA_INT1_MSK		(1 << 24)

#define COBALT_SYSSTAT_VOHSMA_PLL_LOCKED_MSK	(1 << 25)

#define COBALT_SYSSTAT_VOHSMA_LOST_DATA_MSK	(1 << 26)

#define COBALT_SYSSTAT_AUD_PLL_LOCKED_MSK	(1 << 28)

#define COBALT_SYSSTAT_AUD_IN_LOST_DATA_MSK	(1 << 29)

#define COBALT_SYSSTAT_AUD_OUT_LOST_DATA_MSK	(1 << 30)

#define COBALT_SYSSTAT_PCIE_SMBCLK_MSK		(1 << 31)

#define COBALT_SYSSTAT_DIP0_MSK			BIT(0)

#define COBALT_SYSSTAT_DIP1_MSK			BIT(1)

#define COBALT_SYSSTAT_HSMA_PRSNTN_MSK		BIT(2)

#define COBALT_SYSSTAT_FLASH_RDYBSYN_MSK	BIT(3)

#define COBALT_SYSSTAT_VI0_5V_MSK		BIT(4)

#define COBALT_SYSSTAT_VI0_INT1_MSK		BIT(5)

#define COBALT_SYSSTAT_VI0_INT2_MSK		BIT(6)

#define COBALT_SYSSTAT_VI0_LOST_DATA_MSK	BIT(7)

#define COBALT_SYSSTAT_VI1_5V_MSK		BIT(8)

#define COBALT_SYSSTAT_VI1_INT1_MSK		BIT(9)

#define COBALT_SYSSTAT_VI1_INT2_MSK		BIT(10)

#define COBALT_SYSSTAT_VI1_LOST_DATA_MSK	BIT(11)

#define COBALT_SYSSTAT_VI2_5V_MSK		BIT(12)

#define COBALT_SYSSTAT_VI2_INT1_MSK		BIT(13)

#define COBALT_SYSSTAT_VI2_INT2_MSK		BIT(14)

#define COBALT_SYSSTAT_VI2_LOST_DATA_MSK	BIT(15)

#define COBALT_SYSSTAT_VI3_5V_MSK		BIT(16)

#define COBALT_SYSSTAT_VI3_INT1_MSK		BIT(17)

#define COBALT_SYSSTAT_VI3_INT2_MSK		BIT(18)

#define COBALT_SYSSTAT_VI3_LOST_DATA_MSK	BIT(19)

#define COBALT_SYSSTAT_VIHSMA_5V_MSK		BIT(20)

#define COBALT_SYSSTAT_VIHSMA_INT1_MSK		BIT(21)

#define COBALT_SYSSTAT_VIHSMA_INT2_MSK		BIT(22)

#define COBALT_SYSSTAT_VIHSMA_LOST_DATA_MSK	BIT(23)

#define COBALT_SYSSTAT_VOHSMA_INT1_MSK		BIT(24)

#define COBALT_SYSSTAT_VOHSMA_PLL_LOCKED_MSK	BIT(25)

#define COBALT_SYSSTAT_VOHSMA_LOST_DATA_MSK	BIT(26)

#define COBALT_SYSSTAT_AUD_PLL_LOCKED_MSK	BIT(28)

#define COBALT_SYSSTAT_AUD_IN_LOST_DATA_MSK	BIT(29)

#define COBALT_SYSSTAT_AUD_OUT_LOST_DATA_MSK	BIT(30)

#define COBALT_SYSSTAT_PCIE_SMBCLK_MSK		BIT(31)



/* Cobalt memory map */

#define COBALT_I2C_0_BASE			0x0

drivers/media/pci/ivtv/ivtv-irq.h

+14 −14
Original line number Diff line number Diff line
@@ -10,20 +10,20 @@ 
#ifndef IVTV_IRQ_H

#define IVTV_IRQ_H



#define IVTV_IRQ_ENC_START_CAP		(0x1 << 31)

#define IVTV_IRQ_ENC_EOS		(0x1 << 30)

#define IVTV_IRQ_ENC_VBI_CAP		(0x1 << 29)

#define IVTV_IRQ_ENC_VIM_RST		(0x1 << 28)

#define IVTV_IRQ_ENC_DMA_COMPLETE	(0x1 << 27)

#define IVTV_IRQ_ENC_PIO_COMPLETE	(0x1 << 25)

#define IVTV_IRQ_DEC_AUD_MODE_CHG	(0x1 << 24)

#define IVTV_IRQ_DEC_DATA_REQ		(0x1 << 22)

#define IVTV_IRQ_DEC_DMA_COMPLETE	(0x1 << 20)

#define IVTV_IRQ_DEC_VBI_RE_INSERT	(0x1 << 19)

#define IVTV_IRQ_DMA_ERR		(0x1 << 18)

#define IVTV_IRQ_DMA_WRITE		(0x1 << 17)

#define IVTV_IRQ_DMA_READ		(0x1 << 16)

#define IVTV_IRQ_DEC_VSYNC		(0x1 << 10)

#define IVTV_IRQ_ENC_START_CAP		BIT(31)

#define IVTV_IRQ_ENC_EOS		BIT(30)

#define IVTV_IRQ_ENC_VBI_CAP		BIT(29)

#define IVTV_IRQ_ENC_VIM_RST		BIT(28)

#define IVTV_IRQ_ENC_DMA_COMPLETE	BIT(27)

#define IVTV_IRQ_ENC_PIO_COMPLETE	BIT(25)

#define IVTV_IRQ_DEC_AUD_MODE_CHG	BIT(24)

#define IVTV_IRQ_DEC_DATA_REQ		BIT(22)

#define IVTV_IRQ_DEC_DMA_COMPLETE	BIT(20)

#define IVTV_IRQ_DEC_VBI_RE_INSERT	BIT(19)

#define IVTV_IRQ_DMA_ERR		BIT(18)

#define IVTV_IRQ_DMA_WRITE		BIT(17)

#define IVTV_IRQ_DMA_READ		BIT(16)

#define IVTV_IRQ_DEC_VSYNC		BIT(10)



/* IRQ Masks */

#define IVTV_IRQ_MASK_INIT (IVTV_IRQ_DMA_ERR|IVTV_IRQ_ENC_DMA_COMPLETE|\

drivers/media/pci/mantis/mantis_reg.h

+76 −76
Original line number Diff line number Diff line
@@ -14,44 +14,44 @@ 
#define MANTIS_INT_MASK			0x04



#define MANTIS_INT_RISCSTAT		(0x0f << 28)

#define MANTIS_INT_RISCEN		(0x01 << 27)

#define MANTIS_INT_I2CRACK		(0x01 << 26)

#define MANTIS_INT_RISCEN		BIT(27)

#define MANTIS_INT_I2CRACK		BIT(26)



/* #define MANTIS_INT_GPIF			(0xff << 12) */



#define MANTIS_INT_PCMCIA7		(0x01 << 19)

#define MANTIS_INT_PCMCIA6		(0x01 << 18)

#define MANTIS_INT_PCMCIA5		(0x01 << 17)

#define MANTIS_INT_PCMCIA4		(0x01 << 16)

#define MANTIS_INT_PCMCIA3		(0x01 << 15)

#define MANTIS_INT_PCMCIA2		(0x01 << 14)

#define MANTIS_INT_PCMCIA1		(0x01 << 13)

#define MANTIS_INT_PCMCIA0		(0x01 << 12)

#define MANTIS_INT_IRQ1			(0x01 << 11)

#define MANTIS_INT_IRQ0			(0x01 << 10)

#define MANTIS_INT_OCERR		(0x01 <<  8)

#define MANTIS_INT_PABORT		(0x01 <<  7)

#define MANTIS_INT_RIPERR		(0x01 <<  6)

#define MANTIS_INT_PPERR		(0x01 <<  5)

#define MANTIS_INT_FTRGT		(0x01 <<  3)

#define MANTIS_INT_RISCI		(0x01 <<  1)

#define MANTIS_INT_I2CDONE		(0x01 <<  0)

#define MANTIS_INT_PCMCIA7		BIT(19)

#define MANTIS_INT_PCMCIA6		BIT(18)

#define MANTIS_INT_PCMCIA5		BIT(17)

#define MANTIS_INT_PCMCIA4		BIT(16)

#define MANTIS_INT_PCMCIA3		BIT(15)

#define MANTIS_INT_PCMCIA2		BIT(14)

#define MANTIS_INT_PCMCIA1		BIT(13)

#define MANTIS_INT_PCMCIA0		BIT(12)

#define MANTIS_INT_IRQ1			BIT(11)

#define MANTIS_INT_IRQ0			BIT(10)

#define MANTIS_INT_OCERR		BIT(8)

#define MANTIS_INT_PABORT		BIT(7)

#define MANTIS_INT_RIPERR		BIT(6)

#define MANTIS_INT_PPERR		BIT(5)

#define MANTIS_INT_FTRGT		BIT(3)

#define MANTIS_INT_RISCI		BIT(1)

#define MANTIS_INT_I2CDONE		BIT(0)



/* DMA */

#define MANTIS_DMA_CTL			0x08

#define MANTIS_GPIF_RD			(0xff << 24)

#define MANTIS_GPIF_WR			(0xff << 16)

#define MANTIS_CPU_DO			(0x01 << 10)

#define MANTIS_DRV_DO			(0x01 <<  9)

#define	MANTIS_I2C_RD			(0x01 <<  7)

#define MANTIS_I2C_WR			(0x01 <<  6)

#define MANTIS_DCAP_MODE		(0x01 <<  5)

#define MANTIS_CPU_DO			BIT(10)

#define MANTIS_DRV_DO			BIT(9)

#define	MANTIS_I2C_RD			BIT(7)

#define MANTIS_I2C_WR			BIT(6)

#define MANTIS_DCAP_MODE		BIT(5)

#define MANTIS_FIFO_TP_4		(0x00 <<  3)

#define MANTIS_FIFO_TP_8		(0x01 <<  3)

#define MANTIS_FIFO_TP_16		(0x02 <<  3)

#define MANTIS_FIFO_EN			(0x01 <<  2)

#define MANTIS_DCAP_EN			(0x01 <<  1)

#define MANTIS_RISC_EN			(0x01 <<  0)

#define MANTIS_FIFO_EN			BIT(2)

#define MANTIS_DCAP_EN			BIT(1)

#define MANTIS_RISC_EN			BIT(0)



/* DEBUG */

#define MANTIS_DEBUGREG			0x0c
@@ -68,8 +68,8 @@ 
#define MANTIS_I2C_RATE_2		(0x01 <<  6)

#define MANTIS_I2C_RATE_3		(0x02 <<  6)

#define MANTIS_I2C_RATE_4		(0x03 <<  6)

#define MANTIS_I2C_STOP			(0x01 <<  5)

#define MANTIS_I2C_PGMODE		(0x01 <<  3)

#define MANTIS_I2C_STOP			BIT(5)

#define MANTIS_I2C_PGMODE		BIT(3)



/* DATA */

#define MANTIS_CMD_DATA_R1		0x20
@@ -85,77 +85,77 @@ 
#define MANTIS_CMD_DATA_4		(0xff <<  0)



#define MANTIS_CONTROL			0x28

#define MANTIS_DET			(0x01 <<  7)

#define MANTIS_DAT_CF_EN		(0x01 <<  6)

#define MANTIS_DET			BIT(7)

#define MANTIS_DAT_CF_EN		BIT(6)

#define MANTIS_ACS			(0x03 <<  4)

#define MANTIS_VCCEN			(0x01 <<  3)

#define MANTIS_BYPASS			(0x01 <<  2)

#define MANTIS_MRST			(0x01 <<  1)

#define MANTIS_CRST_INT			(0x01 <<  0)

#define MANTIS_VCCEN			BIT(3)

#define MANTIS_BYPASS			BIT(2)

#define MANTIS_MRST			BIT(1)

#define MANTIS_CRST_INT			BIT(0)



#define MANTIS_GPIF_CFGSLA		0x84

#define MANTIS_GPIF_WAITSMPL		(0x07 << 28)

#define MANTIS_GPIF_BYTEADDRSUB		(0x01 << 25)

#define MANTIS_GPIF_WAITPOL		(0x01 << 24)

#define MANTIS_GPIF_BYTEADDRSUB		BIT(25)

#define MANTIS_GPIF_WAITPOL		BIT(24)

#define MANTIS_GPIF_NCDELAY		(0x07 << 20)

#define MANTIS_GPIF_RW2CSDELAY		(0x07 << 16)

#define MANTIS_GPIF_SLFTIMEDMODE	(0x01 << 15)

#define MANTIS_GPIF_SLFTIMEDMODE	BIT(15)

#define MANTIS_GPIF_SLFTIMEDDELY	(0x7f <<  8)

#define MANTIS_GPIF_DEVTYPE		(0x07 <<  4)

#define MANTIS_GPIF_BIGENDIAN		(0x01 <<  3)

#define MANTIS_GPIF_BIGENDIAN		BIT(3)

#define MANTIS_GPIF_FETCHCMD		(0x03 <<  1)

#define MANTIS_GPIF_HWORDDEV		(0x01 <<  0)

#define MANTIS_GPIF_HWORDDEV		BIT(0)



#define MANTIS_GPIF_WSTOPER		0x90

#define MANTIS_GPIF_WSTOPERWREN3	(0x01 << 31)

#define MANTIS_GPIF_PARBOOTN		(0x01 << 29)

#define MANTIS_GPIF_WSTOPERWREN3	BIT(31)

#define MANTIS_GPIF_PARBOOTN		BIT(29)

#define MANTIS_GPIF_WSTOPERSLID3	(0x1f << 24)

#define MANTIS_GPIF_WSTOPERWREN2	(0x01 << 23)

#define MANTIS_GPIF_WSTOPERWREN2	BIT(23)

#define MANTIS_GPIF_WSTOPERSLID2	(0x1f << 16)

#define MANTIS_GPIF_WSTOPERWREN1	(0x01 << 15)

#define MANTIS_GPIF_WSTOPERWREN1	BIT(15)

#define MANTIS_GPIF_WSTOPERSLID1	(0x1f <<  8)

#define MANTIS_GPIF_WSTOPERWREN0	(0x01 <<  7)

#define MANTIS_GPIF_WSTOPERWREN0	BIT(7)

#define MANTIS_GPIF_WSTOPERSLID0	(0x1f <<  0)



#define MANTIS_GPIF_CS2RW		0x94

#define MANTIS_GPIF_CS2RWWREN3		(0x01 << 31)

#define MANTIS_GPIF_CS2RWWREN3		BIT(31)

#define MANTIS_GPIF_CS2RWDELY3		(0x3f << 24)

#define MANTIS_GPIF_CS2RWWREN2		(0x01 << 23)

#define MANTIS_GPIF_CS2RWWREN2		BIT(23)

#define MANTIS_GPIF_CS2RWDELY2		(0x3f << 16)

#define MANTIS_GPIF_CS2RWWREN1		(0x01 << 15)

#define MANTIS_GPIF_CS2RWWREN1		BIT(15)

#define MANTIS_GPIF_CS2RWDELY1		(0x3f <<  8)

#define MANTIS_GPIF_CS2RWWREN0		(0x01 <<  7)

#define MANTIS_GPIF_CS2RWWREN0		BIT(7)

#define MANTIS_GPIF_CS2RWDELY0		(0x3f <<  0)



#define MANTIS_GPIF_IRQCFG		0x98

#define MANTIS_GPIF_IRQPOL		(0x01 <<  8)

#define MANTIS_MASK_WRACK		(0x01 <<  7)

#define MANTIS_MASK_BRRDY		(0x01 <<  6)

#define MANTIS_MASK_OVFLW		(0x01 <<  5)

#define MANTIS_MASK_OTHERR		(0x01 <<  4)

#define MANTIS_MASK_WSTO		(0x01 <<  3)

#define MANTIS_MASK_EXTIRQ		(0x01 <<  2)

#define MANTIS_MASK_PLUGIN		(0x01 <<  1)

#define MANTIS_MASK_PLUGOUT		(0x01 <<  0)

#define MANTIS_GPIF_IRQPOL		BIT(8)

#define MANTIS_MASK_WRACK		BIT(7)

#define MANTIS_MASK_BRRDY		BIT(6)

#define MANTIS_MASK_OVFLW		BIT(5)

#define MANTIS_MASK_OTHERR		BIT(4)

#define MANTIS_MASK_WSTO		BIT(3)

#define MANTIS_MASK_EXTIRQ		BIT(2)

#define MANTIS_MASK_PLUGIN		BIT(1)

#define MANTIS_MASK_PLUGOUT		BIT(0)



#define MANTIS_GPIF_STATUS		0x9c

#define MANTIS_SBUF_KILLOP		(0x01 << 15)

#define MANTIS_SBUF_OPDONE		(0x01 << 14)

#define MANTIS_SBUF_EMPTY		(0x01 << 13)

#define MANTIS_GPIF_DETSTAT		(0x01 <<  9)

#define MANTIS_GPIF_INTSTAT		(0x01 <<  8)

#define MANTIS_GPIF_WRACK		(0x01 <<  7)

#define MANTIS_GPIF_BRRDY		(0x01 <<  6)

#define MANTIS_SBUF_OVFLW		(0x01 <<  5)

#define MANTIS_GPIF_OTHERR		(0x01 <<  4)

#define MANTIS_SBUF_WSTO		(0x01 <<  3)

#define MANTIS_GPIF_EXTIRQ		(0x01 <<  2)

#define MANTIS_CARD_PLUGIN		(0x01 <<  1)

#define MANTIS_CARD_PLUGOUT		(0x01 <<  0)

#define MANTIS_SBUF_KILLOP		BIT(15)

#define MANTIS_SBUF_OPDONE		BIT(14)

#define MANTIS_SBUF_EMPTY		BIT(13)

#define MANTIS_GPIF_DETSTAT		BIT(9)

#define MANTIS_GPIF_INTSTAT		BIT(8)

#define MANTIS_GPIF_WRACK		BIT(7)

#define MANTIS_GPIF_BRRDY		BIT(6)

#define MANTIS_SBUF_OVFLW		BIT(5)

#define MANTIS_GPIF_OTHERR		BIT(4)

#define MANTIS_SBUF_WSTO		BIT(3)

#define MANTIS_GPIF_EXTIRQ		BIT(2)

#define MANTIS_CARD_PLUGIN		BIT(1)

#define MANTIS_CARD_PLUGOUT		BIT(0)



#define MANTIS_GPIF_BRADDR		0xa0

#define MANTIS_GPIF_PCMCIAREG		(0x01		<< 27)

#define MANTIS_GPIF_PCMCIAIOM		(0x01		<< 26)

#define MANTIS_GPIF_PCMCIAREG		BIT(27)

#define MANTIS_GPIF_PCMCIAIOM		BIT(26)

#define MANTIS_GPIF_BR_ADDR		(0xfffffff	<<  0)



#define MANTIS_GPIF_BRBYTES		0xa4
@@ -167,9 +167,9 @@ 
#define MANTIS_CARD_RESET		0xac



#define MANTIS_GPIF_ADDR		0xb0

#define MANTIS_GPIF_HIFRDWRN		(0x01		<< 31)

#define MANTIS_GPIF_PCMCIAREG		(0x01		<< 27)

#define MANTIS_GPIF_PCMCIAIOM		(0x01		<< 26)

#define MANTIS_GPIF_HIFRDWRN		BIT(31)

#define MANTIS_GPIF_PCMCIAREG		BIT(27)

#define MANTIS_GPIF_PCMCIAIOM		BIT(26)

#define MANTIS_GPIF_HIFADDR		(0xfffffff	<<  0)



#define MANTIS_GPIF_DOUT		0xb4

drivers/media/pci/solo6x10/solo6x10-regs.h

+144 −142

File changed.

Preview size limit exceeded, changes collapsed.

drivers/media/platform/am437x/am437x-vpfe_regs.h

+13 −13
Original line number Diff line number Diff line
@@ -66,13 +66,13 @@ 
#define VPFE_PIX_FMT_MASK			3

#define VPFE_PIX_FMT_SHIFT			12

#define VPFE_VP2SDR_DISABLE			0xfffbffff

#define VPFE_WEN_ENABLE				(1 << 17)

#define VPFE_WEN_ENABLE				BIT(17)

#define VPFE_SDR2RSZ_DISABLE			0xfff7ffff

#define VPFE_VDHDEN_ENABLE			(1 << 16)

#define VPFE_LPF_ENABLE				(1 << 14)

#define VPFE_ALAW_ENABLE			(1 << 3)

#define VPFE_VDHDEN_ENABLE			BIT(16)

#define VPFE_LPF_ENABLE				BIT(14)

#define VPFE_ALAW_ENABLE			BIT(3)

#define VPFE_ALAW_GAMMA_WD_MASK			7

#define VPFE_BLK_CLAMP_ENABLE			(1 << 31)

#define VPFE_BLK_CLAMP_ENABLE			BIT(31)

#define VPFE_BLK_SGAIN_MASK			0x1f

#define VPFE_BLK_ST_PXL_MASK			0x7fff

#define VPFE_BLK_ST_PXL_SHIFT			10
@@ -85,8 +85,8 @@ 
#define VPFE_BLK_COMP_GB_COMP_SHIFT		8

#define VPFE_BLK_COMP_GR_COMP_SHIFT		16

#define VPFE_BLK_COMP_R_COMP_SHIFT		24

#define VPFE_LATCH_ON_VSYNC_DISABLE		(1 << 15)

#define VPFE_DATA_PACK_ENABLE			(1 << 11)

#define VPFE_LATCH_ON_VSYNC_DISABLE		BIT(15)

#define VPFE_DATA_PACK_ENABLE			BIT(11)

#define VPFE_HORZ_INFO_SPH_SHIFT		16

#define VPFE_VERT_START_SLV0_SHIFT		16

#define VPFE_VDINT_VDINT0_SHIFT			16
@@ -114,15 +114,15 @@ 
#define VPFE_SYN_FLDMODE_MASK			1

#define VPFE_SYN_FLDMODE_SHIFT			7

#define VPFE_REC656IF_BT656_EN			3

#define VPFE_SYN_MODE_VD_POL_NEGATIVE		(1 << 2)

#define VPFE_SYN_MODE_VD_POL_NEGATIVE		BIT(2)

#define VPFE_CCDCFG_Y8POS_SHIFT			11

#define VPFE_CCDCFG_BW656_10BIT			(1 << 5)

#define VPFE_CCDCFG_BW656_10BIT			BIT(5)

#define VPFE_SDOFST_FIELD_INTERLEAVED		0x249

#define VPFE_NO_CULLING				0xffff00ff

#define VPFE_VDINT0				(1 << 0)

#define VPFE_VDINT1				(1 << 1)

#define VPFE_VDINT2				(1 << 2)

#define VPFE_DMA_CNTL_OVERFLOW			(1 << 31)

#define VPFE_VDINT0				BIT(0)

#define VPFE_VDINT1				BIT(1)

#define VPFE_VDINT2				BIT(2)

#define VPFE_DMA_CNTL_OVERFLOW			BIT(31)



#define VPFE_CONFIG_PCLK_INV_SHIFT		0

#define VPFE_CONFIG_PCLK_INV_MASK		1

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