Unverified Commit ccd51b9f authored by Paul Burton's avatar Paul Burton
Browse files

MIPS: Remove unused R5432_CP0_INTERRUPT_WAR 



R5432_CP0_INTERRUPT_WAR is defined as 0 for every system we support, and
so the workaround is never used. Remove the dead code.

Signed-off-by: default avatarPaul Burton <paul.burton@mips.com>
Cc: linux-mips@vger.kernel.org
parent 8e96b084

arch/mips/include/asm/mach-cavium-octeon/war.h

+0 −1
Original line number Diff line number Diff line
@@ -12,7 +12,6 @@ 
#define R4600_V1_INDEX_ICACHEOP_WAR	0

#define R4600_V1_HIT_CACHEOP_WAR	0

#define R4600_V2_HIT_CACHEOP_WAR	0

#define R5432_CP0_INTERRUPT_WAR		0

#define BCM1250_M3_WAR			0

#define SIBYTE_1956_WAR			0

#define MIPS4K_ICACHE_REFILL_WAR	0

arch/mips/include/asm/mach-generic/war.h

+0 −1
Original line number Diff line number Diff line
@@ -11,7 +11,6 @@ 
#define R4600_V1_INDEX_ICACHEOP_WAR	0

#define R4600_V1_HIT_CACHEOP_WAR	0

#define R4600_V2_HIT_CACHEOP_WAR	0

#define R5432_CP0_INTERRUPT_WAR		0

#define BCM1250_M3_WAR			0

#define SIBYTE_1956_WAR			0

#define MIPS4K_ICACHE_REFILL_WAR	0

arch/mips/include/asm/mach-ip22/war.h

+0 −1
Original line number Diff line number Diff line
@@ -15,7 +15,6 @@ 
#define R4600_V1_INDEX_ICACHEOP_WAR	1

#define R4600_V1_HIT_CACHEOP_WAR	1

#define R4600_V2_HIT_CACHEOP_WAR	1

#define R5432_CP0_INTERRUPT_WAR		0

#define BCM1250_M3_WAR			0

#define SIBYTE_1956_WAR			0

#define MIPS4K_ICACHE_REFILL_WAR	0

arch/mips/include/asm/mach-ip27/war.h

+0 −1
Original line number Diff line number Diff line
@@ -11,7 +11,6 @@ 
#define R4600_V1_INDEX_ICACHEOP_WAR	0

#define R4600_V1_HIT_CACHEOP_WAR	0

#define R4600_V2_HIT_CACHEOP_WAR	0

#define R5432_CP0_INTERRUPT_WAR		0

#define BCM1250_M3_WAR			0

#define SIBYTE_1956_WAR			0

#define MIPS4K_ICACHE_REFILL_WAR	0

arch/mips/include/asm/mach-ip28/war.h

+0 −1
Original line number Diff line number Diff line
@@ -11,7 +11,6 @@ 
#define R4600_V1_INDEX_ICACHEOP_WAR	0

#define R4600_V1_HIT_CACHEOP_WAR	0

#define R4600_V2_HIT_CACHEOP_WAR	0

#define R5432_CP0_INTERRUPT_WAR		0

#define BCM1250_M3_WAR			0

#define SIBYTE_1956_WAR			0

#define MIPS4K_ICACHE_REFILL_WAR	0

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