Merge tag 'v4.0-next-dts' of https://github.com/mbgg/linux-mediatek into next/dt

MediaTek PMIC Wrapper Driver

This document describes the binding for the MediaTek PMIC wrapper.

On MediaTek SoCs the PMIC is connected via SPI. The SPI master interface

is not directly visible to the CPU, but only through the PMIC wrapper

inside the SoC. The communication between the SoC and the PMIC can

optionally be encrypted. Also a non standard Dual IO SPI mode can be

used to increase speed.

IP Pairing

on MT8135 the pins of some SoC internal peripherals can be on the PMIC.

The signals of these pins are routed over the SPI bus using the pwrap

bridge. In the binding description below the properties needed for bridging

are marked with "IP Pairing". These are optional on SoCs which do not support

IP Pairing

Required properties in pwrap device node.

- compatible:

	"mediatek,mt8135-pwrap" for MT8135 SoCs

	"mediatek,mt8173-pwrap" for MT8173 SoCs

- interrupts: IRQ for pwrap in SOC

- reg-names: Must include the following entries:

  "pwrap": Main registers base

  "pwrap-bridge": bridge base (IP Pairing)

- reg: Must contain an entry for each entry in reg-names.

- reset-names: Must include the following entries:

  "pwrap"

  "pwrap-bridge" (IP Pairing)

- resets: Must contain an entry for each entry in reset-names.

- clock-names: Must include the following entries:

  "spi": SPI bus clock

  "wrap": Main module clock

- clocks: Must contain an entry for each entry in clock-names.

Optional properities:

- pmic: Mediatek PMIC MFD is the child device of pwrap

  See the following for child node definitions:

  Documentation/devicetree/bindings/mfd/mt6397.txt

Example:

	pwrap: pwrap@1000f000 {

		compatible = "mediatek,mt8135-pwrap";

		reg = <0 0x1000f000 0 0x1000>,

			<0 0x11017000 0 0x1000>;

		reg-names = "pwrap", "pwrap-bridge";

		interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;

		resets = <&infracfg MT8135_INFRA_PMIC_WRAP_RST>,

				<&pericfg MT8135_PERI_PWRAP_BRIDGE_SW_RST>;

		reset-names = "pwrap", "pwrap-bridge";

		clocks = <&clk26m>, <&clk26m>;

		clock-names = "spi", "wrap";

		pmic {

			compatible = "mediatek,mt6397";

		};

	};

			clocks = <&uart_clk>;

			status = "disabled";

		};

		wdt: watchdog@010000000 {

			compatible = "mediatek,mt6589-wdt";

			reg = <0x10000000 0x44>;

		};

	};

};

#include <dt-bindings/interrupt-controller/irq.h>

#include <dt-bindings/interrupt-controller/arm-gic.h>

#include "skeleton64.dtsi"

#include "mt8135-pinfunc.h"

/ {

	compatible = "mediatek,mt8135";

		compatible = "simple-bus";

		ranges;

		syscfg_pctl_a: syscfg_pctl_a@10005000 {

			compatible = "mediatek,mt8135-pctl-a-syscfg", "syscon";

			reg = <0 0x10005000 0 0x1000>;

		};

		syscfg_pctl_b: syscfg_pctl_b@1020C000 {

			compatible = "mediatek,mt8135-pctl-b-syscfg", "syscon";

			reg = <0 0x1020C000 0 0x1000>;

		};

		pio: pinctrl@10005000 {

			compatible = "mediatek,mt8135-pinctrl";

			reg = <0 0x1000B000 0 0x1000>;

			mediatek,pctl-regmap = <&syscfg_pctl_a &syscfg_pctl_b>;

			pins-are-numbered;

			gpio-controller;

			#gpio-cells = <2>;

			interrupt-controller;

			#interrupt-cells = <2>;

			interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;

		};

		timer: timer@10008000 {

			compatible = "mediatek,mt8135-timer",

					"mediatek,mt6577-timer";