Commit cca3731e authored by Dinh Nguyen's avatar Dinh Nguyen
Browse files

ARM: dts: socfpga: use the "altr,socfpga-stmmac-a10-s10" binding 



Because of register and bits difference for setting PHY modes, PTP reference
clock, and FPGA signalling, the Arria10 SoC needs to use the
"altr,socfpga-stmmac-a10-s10" binding to set the correct modes.

On Arria10, each EMAC has its own register for PHY modes, and they all have
the same offset, thus we can use the 2nd parameter to specify the offsets
for the FPGA signal bits.

Signed-off-by: default avatarDinh Nguyen <dinguyen@kernel.org>
parent a188339c

arch/arm/boot/dts/socfpga_arria10.dtsi

+5 −5
Original line number Diff line number Diff line
@@ -418,7 +418,7 @@ 
		};



		gmac0: ethernet@ff800000 {

			compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac";

			compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.72a", "snps,dwmac";

			altr,sysmgr-syscon = <&sysmgr 0x44 0>;

			reg = <0xff800000 0x2000>;

			interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
@@ -438,8 +438,8 @@ 
		};



		gmac1: ethernet@ff802000 {

			compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac";

			altr,sysmgr-syscon = <&sysmgr 0x48 0>;

			compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.72a", "snps,dwmac";

			altr,sysmgr-syscon = <&sysmgr 0x48 8>;

		        reg = <0xff802000 0x2000>;

			interrupts = <0 93 IRQ_TYPE_LEVEL_HIGH>;

			interrupt-names = "macirq";
@@ -458,8 +458,8 @@ 
		};



		gmac2: ethernet@ff804000 {

			compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac";

			altr,sysmgr-syscon = <&sysmgr 0x4C 0>;

			compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.72a", "snps,dwmac";

			altr,sysmgr-syscon = <&sysmgr 0x4C 16>;

			reg = <0xff804000 0x2000>;

			interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;

			interrupt-names = "macirq";

CRA Git | Maintained and supported by SUSTech CRA and CCSE