Commit cc7b9904 authored by Olof Johansson's avatar Olof Johansson
Browse files

Merge tag 'renesas-dt-for-v3.17' of... 

Merge tag 'renesas-dt-for-v3.17' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/dt

Merge "Renesas ARM Based SoC DT Updates for v3.17" from Simon Horman:

Increased hardware coverage:
- Add R-Car sounds support to r8a7790 SoC
- Add PCIe support to r8a7790 and r8a7791 SoCs
- Increase I2C support of Henninger and lager boards
- DVFS support to Koelsch board
- Add SYS-DMAC clocks to r8a7791 SoCs
- Add USB 3.0 clocks to r8a7791 and r8a7790 SoCs
- Add LED labels to armadillo800eva board

Cleanup:
- Remove early_printk from marzen command line

* tag 'renesas-dt-for-v3.17' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas

: (29 commits)
  ARM: shmobile: r8a7791: add R-Car sound support on DTSI
  ARM: shmobile: henninger: Enable PCIe Controller & PCIe bus clock
  ARM: shmobile: koelsch: Enable PCIe Controller & PCIe bus clock
  ARM: shmobile: r8a7791: Add PCIe Controller device node
  ARM: shmobile: r8a7791: Add default PCIe bus clock
  ARM: shmobile: r8a7791: Add PCIEC clock device tree node
  ARM: shmobile: r8a7790: Add PCIe Controller device node
  ARM: shmobile: r8a7790: Add default PCIe bus clock
  ARM: shmobile: r8a7790: Add PCIEC clock device tree node
  ARM: shmobile: r8a7791: add MSTP10 support on DTSI
  ARM: shmobile: r8a7791: add audio clock on DTSI
  ARM: shmobile: r8a7790: add R-Car sound support on DTSI
  ARM: shmobile: r8a7790: add MSTP10 support on DTSI
  ARM: shmobile: henninger: add I2C2 DT support
  ARM: shmobile: koelsch: Remove duplicate i2c6 nodes
  ARM: shmobile: lager: Remove duplicate i2c3 nodes
  ARM: shmobile: Lager memory map update
  ARM: shmobile: lager: Move i2c[12]_pins nodes to pfc node
  ARM: shmobile: lager: add i2c1, i2c2 pins
  ARM: shmobile: lager: enable i2c devices
  ...

Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parents 4c834452 09abd1fd

arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts

+8 −4
Original line number Diff line number Diff line
@@ -104,17 +104,21 @@ 


	leds {

		compatible = "gpio-leds";

		led1 {

		led3 {

			gpios = <&pfc 102 GPIO_ACTIVE_HIGH>;

			label = "LED3";

		};

		led2 {

		led4 {

			gpios = <&pfc 111 GPIO_ACTIVE_HIGH>;

			label = "LED4";

		};

		led3 {

		led5 {

			gpios = <&pfc 110 GPIO_ACTIVE_HIGH>;

			label = "LED5";

		};

		led4 {

		led6 {

			gpios = <&pfc 177 GPIO_ACTIVE_HIGH>;

			label = "LED6";

		};

	};

arch/arm/boot/dts/r8a7779-marzen.dts

+1 −1
Original line number Diff line number Diff line
@@ -17,7 +17,7 @@ 
	compatible = "renesas,marzen", "renesas,r8a7779";



	chosen {

		bootargs = "console=ttySC2,115200 earlyprintk=sh-sci.2,115200 ignore_loglevel root=/dev/nfs ip=on";

		bootargs = "console=ttySC2,115200 ignore_loglevel root=/dev/nfs ip=on";

	};



	memory {

arch/arm/boot/dts/r8a7790-lager.dts

+53 −2
Original line number Diff line number Diff line
@@ -29,12 +29,12 @@ 


	memory@40000000 {

		device_type = "memory";

		reg = <0 0x40000000 0 0x80000000>;

		reg = <0 0x40000000 0 0x40000000>;

	};



	memory@180000000 {

		device_type = "memory";

		reg = <1 0x80000000 0 0x80000000>;

		reg = <1 0x40000000 0 0xc0000000>;

	};



	lbsc {
@@ -204,6 +204,21 @@ 
				 "msiof1_tx";

		renesas,function = "msiof1";

	};



	i2c1_pins: i2c1 {

		renesas,groups = "i2c1";

		renesas,function = "i2c1";

	};



	i2c2_pins: i2c2 {

		renesas,groups = "i2c2";

		renesas,function = "i2c2";

	};



	i2c3_pins: i2c3 {

		renesas,groups = "i2c3";

		renesas,function = "i2c3";

	};

};



&ether {
@@ -317,3 +332,39 @@ 
	cd-gpios = <&gpio3 22 GPIO_ACTIVE_LOW>;

	status = "okay";

};



&cpu0 {

	cpu0-supply = <&vdd_dvfs>;

};



&i2c0	{

	status = "ok";

};



&i2c1	{

	status = "ok";

	pinctrl-0 = <&i2c1_pins>;

	pinctrl-names = "default";

};



&i2c2	{

	status = "ok";

	pinctrl-0 = <&i2c2_pins>;

	pinctrl-names = "default";

};



&i2c3 {

	pinctrl-names = "default";

	pinctrl-0 = <&i2c3_pins>;

	status = "okay";



	vdd_dvfs: regulator@68 {

		compatible = "diasemi,da9210";

		reg = <0x68>;



		regulator-min-microvolt = <1000000>;

		regulator-max-microvolt = <1000000>;

		regulator-boot-on;

		regulator-always-on;

	};

};

arch/arm/boot/dts/r8a7790.dtsi

+137 −3
Original line number Diff line number Diff line
@@ -44,6 +44,17 @@ 
			compatible = "arm,cortex-a15";

			reg = <0>;

			clock-frequency = <1300000000>;

			voltage-tolerance = <1>; /* 1% */

			clocks = <&cpg_clocks R8A7790_CLK_Z>;

			clock-latency = <300000>; /* 300 us */



			/* kHz - uV - OPPs unknown yet */

			operating-points = <1400000 1000000>,

					   <1225000 1000000>,

					   <1050000 1000000>,

					   < 875000 1000000>,

					   < 700000 1000000>,

					   < 350000 1000000>;

		};



		cpu1: cpu@1 {
@@ -476,6 +487,15 @@ 
			clock-output-names = "extal";

		};



		/* External PCIe clock - can be overridden by the board */

		pcie_bus_clk: pcie_bus_clk {

			compatible = "fixed-clock";

			#clock-cells = <0>;

			clock-frequency = <100000000>;

			clock-output-names = "pcie_bus";

			status = "disabled";

		};



		/*

		 * The external audio clocks are configured as 0 Hz fixed frequency clocks by

		 * default. Boards that provide audio clocks should override them.
@@ -754,17 +774,17 @@ 
			reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;

			clocks = <&hp_clk>, <&cp_clk>, <&mmc1_clk>, <&sd3_clk>,

				 <&sd2_clk>, <&cpg_clocks R8A7790_CLK_SD1>, <&cpg_clocks R8A7790_CLK_SD0>, <&mmc0_clk>,

				 <&hp_clk>, <&hp_clk>, <&rclk_clk>;

				 <&hp_clk>, <&mp_clk>, <&hp_clk>, <&mp_clk>, <&rclk_clk>;

			#clock-cells = <1>;

			renesas,clock-indices = <

				R8A7790_CLK_IIC2 R8A7790_CLK_TPU0 R8A7790_CLK_MMCIF1 R8A7790_CLK_SDHI3

				R8A7790_CLK_SDHI2 R8A7790_CLK_SDHI1 R8A7790_CLK_SDHI0 R8A7790_CLK_MMCIF0

				R8A7790_CLK_IIC0 R8A7790_CLK_IIC1 R8A7790_CLK_CMT1

				R8A7790_CLK_IIC0 R8A7790_CLK_PCIEC R8A7790_CLK_IIC1 R8A7790_CLK_SSUSB R8A7790_CLK_CMT1

			>;

			clock-output-names =

				"iic2", "tpu0", "mmcif1", "sdhi3",

				"sdhi2", "sdhi1", "sdhi0", "mmcif0",

				"iic0", "iic1", "cmt1";

				"iic0", "pciec", "iic1", "ssusb", "cmt1";

		};

		mstp5_clks: mstp5_clks@e6150144 {

			compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
@@ -824,6 +844,39 @@ 
				"rcan1", "rcan0", "qspi_mod", "iic3",

				"i2c3", "i2c2", "i2c1", "i2c0";

		};

		mstp10_clks: mstp10_clks@e6150998 {

			compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";

			reg = <0 0xe6150998 0 4>, <0 0xe61509a8 0 4>;

			clocks = <&p_clk>,

				<&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,

				<&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,

				<&p_clk>,

				<&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,

				<&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,

				<&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,

				<&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,

				<&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,

				<&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>;



			#clock-cells = <1>;

			clock-indices = <

				R8A7790_CLK_SSI_ALL

				R8A7790_CLK_SSI9 R8A7790_CLK_SSI8 R8A7790_CLK_SSI7 R8A7790_CLK_SSI6 R8A7790_CLK_SSI5

				R8A7790_CLK_SSI4 R8A7790_CLK_SSI3 R8A7790_CLK_SSI2 R8A7790_CLK_SSI1 R8A7790_CLK_SSI0

				R8A7790_CLK_SCU_ALL

				R8A7790_CLK_SCU_DVC1 R8A7790_CLK_SCU_DVC0

				R8A7790_CLK_SCU_SRC9 R8A7790_CLK_SCU_SRC8 R8A7790_CLK_SCU_SRC7 R8A7790_CLK_SCU_SRC6 R8A7790_CLK_SCU_SRC5

				R8A7790_CLK_SCU_SRC4 R8A7790_CLK_SCU_SRC3 R8A7790_CLK_SCU_SRC2 R8A7790_CLK_SCU_SRC1 R8A7790_CLK_SCU_SRC0

			>;

			clock-output-names =

				"ssi-all",

				"ssi9", "ssi8", "ssi7", "ssi6", "ssi5",

				"ssi4", "ssi3", "ssi2", "ssi1", "ssi0",

				"scu-all",

				"scu-dvc1", "scu-dvc0",

				"scu-src9", "scu-src8", "scu-src7", "scu-src6", "scu-src5",

				"scu-src4", "scu-src3", "scu-src2", "scu-src1", "scu-src0";

		};

	};



	qspi: spi@e6b10000 {
@@ -876,4 +929,85 @@ 
		#size-cells = <0>;

		status = "disabled";

	};



	pciec: pcie@fe000000 {

		compatible = "renesas,pcie-r8a7790";

		reg = <0 0xfe000000 0 0x80000>;

		#address-cells = <3>;

		#size-cells = <2>;

		bus-range = <0x00 0xff>;

		device_type = "pci";

		ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000

			  0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000

			  0x02000000 0 0x30000000 0 0x30000000 0 0x08000000

			  0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;

		/* Map all possible DDR as inbound ranges */

		dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000

			      0x43000000 1 0x80000000 1 0x80000000 0 0x80000000>;

		interrupts = <0 116 IRQ_TYPE_LEVEL_HIGH>,

			     <0 117 IRQ_TYPE_LEVEL_HIGH>,

			     <0 118 IRQ_TYPE_LEVEL_HIGH>;

		#interrupt-cells = <1>;

		interrupt-map-mask = <0 0 0 0>;

		interrupt-map = <0 0 0 0 &gic 0 116 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&mstp3_clks R8A7790_CLK_PCIEC>, <&pcie_bus_clk>;

		clock-names = "pcie", "pcie_bus";

		status = "disabled";

	};



	rcar_sound: rcar_sound@0xec500000 {

		#sound-dai-cells = <1>;

		compatible =  "renesas,rcar_sound-r8a7790", "renesas,rcar_sound-gen2", "renesas,rcar_sound";

		interrupt-parent = <&gic>;

		reg =	<0 0xec500000 0 0x1000>, /* SCU */

			<0 0xec5a0000 0 0x100>,  /* ADG */

			<0 0xec540000 0 0x1000>, /* SSIU */

			<0 0xec541000 0 0x1280>; /* SSI */

		clocks = <&mstp10_clks R8A7790_CLK_SSI_ALL>,

			<&mstp10_clks R8A7790_CLK_SSI9>, <&mstp10_clks R8A7790_CLK_SSI8>,

			<&mstp10_clks R8A7790_CLK_SSI7>, <&mstp10_clks R8A7790_CLK_SSI6>,

			<&mstp10_clks R8A7790_CLK_SSI5>, <&mstp10_clks R8A7790_CLK_SSI4>,

			<&mstp10_clks R8A7790_CLK_SSI3>, <&mstp10_clks R8A7790_CLK_SSI2>,

			<&mstp10_clks R8A7790_CLK_SSI1>, <&mstp10_clks R8A7790_CLK_SSI0>,

			<&mstp10_clks R8A7790_CLK_SCU_SRC9>, <&mstp10_clks R8A7790_CLK_SCU_SRC8>,

			<&mstp10_clks R8A7790_CLK_SCU_SRC7>, <&mstp10_clks R8A7790_CLK_SCU_SRC6>,

			<&mstp10_clks R8A7790_CLK_SCU_SRC5>, <&mstp10_clks R8A7790_CLK_SCU_SRC4>,

			<&mstp10_clks R8A7790_CLK_SCU_SRC3>, <&mstp10_clks R8A7790_CLK_SCU_SRC2>,

			<&mstp10_clks R8A7790_CLK_SCU_SRC1>, <&mstp10_clks R8A7790_CLK_SCU_SRC0>,

			<&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, <&m2_clk>;

		clock-names = "ssi-all",

				"ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5",

				"ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0",

				"src.9", "src.8", "src.7", "src.6", "src.5",

				"src.4", "src.3", "src.2", "src.1", "src.0",

				"clk_a", "clk_b", "clk_c", "clk_i";



		status = "disabled";



		rcar_sound,src {

			src0: src@0 { };

			src1: src@1 { };

			src2: src@2 { };

			src3: src@3 { };

			src4: src@4 { };

			src5: src@5 { };

			src6: src@6 { };

			src7: src@7 { };

			src8: src@8 { };

			src9: src@9 { };

		};



		rcar_sound,ssi {

			ssi0: ssi@0 { interrupts = <0 370 IRQ_TYPE_LEVEL_HIGH>; };

			ssi1: ssi@1 { interrupts = <0 371 IRQ_TYPE_LEVEL_HIGH>; };

			ssi2: ssi@2 { interrupts = <0 372 IRQ_TYPE_LEVEL_HIGH>; };

			ssi3: ssi@3 { interrupts = <0 373 IRQ_TYPE_LEVEL_HIGH>; };

			ssi4: ssi@4 { interrupts = <0 374 IRQ_TYPE_LEVEL_HIGH>; };

			ssi5: ssi@5 { interrupts = <0 375 IRQ_TYPE_LEVEL_HIGH>; };

			ssi6: ssi@6 { interrupts = <0 376 IRQ_TYPE_LEVEL_HIGH>; };

			ssi7: ssi@7 { interrupts = <0 377 IRQ_TYPE_LEVEL_HIGH>; };

			ssi8: ssi@8 { interrupts = <0 378 IRQ_TYPE_LEVEL_HIGH>; };

			ssi9: ssi@9 { interrupts = <0 379 IRQ_TYPE_LEVEL_HIGH>; };

		};

	};

};

arch/arm/boot/dts/r8a7791-henninger.dts

+21 −0
Original line number Diff line number Diff line
@@ -110,6 +110,11 @@ 
		renesas,function = "sdhi2";

	};



	i2c2_pins: i2c2 {

		renesas,groups = "i2c2";

		renesas,function = "i2c2";

	};



	qspi_pins: spi0 {

		renesas,groups = "qspi_ctrl", "qspi_data4";

		renesas,function = "qspi";
@@ -170,6 +175,14 @@ 
	status = "okay";

};



&i2c2 {

	pinctrl-0 = <&i2c2_pins>;

	pinctrl-names = "default";



	status = "okay";

	clock-frequency = <400000>;

};



&qspi {

	pinctrl-0 = <&qspi_pins>;

	pinctrl-names = "default";
@@ -217,3 +230,11 @@ 
		spi-cpha;

	};

};



&pcie_bus_clk {

	status = "okay";

};



&pciec {

	status = "okay";

};

CRA Git | Maintained and supported by SUSTech CRA and CCSE