powerpc/xmon: Update ppc-dis/opc.c and ppc.h (cc7639ce) · Commits · 戴 / test

arch/powerpc/Kconfig.debug

+1 −0

Original line number	Diff line number	Diff line
		@@ -115,6 +115,7 @@ config XMON_DEFAULT
		config XMON_DISASSEMBLY
		bool "Include disassembly support in xmon"
		depends on XMON
		depends on BROKEN
		default y
		help
		Include support for disassembling in xmon. You probably want

arch/powerpc/xmon/ppc-dis.c

+224 −48

Original line number	Diff line number	Diff line
		/* ppc-dis.c -- Disassemble PowerPC instructions
		Copyright 1994, 1995, 2000, 2001, 2002, 2003, 2004, 2005, 2006
		Copyright 1994, 1995, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
		Free Software Foundation, Inc.
		Written by Ian Lance Taylor, Cygnus Support

		@@ -19,34 +19,193 @@ You should have received a copy of the GNU General Public License
		along with this file; see the file COPYING. If not, write to the Free
		Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */

		#include <asm/cputable.h>
		#include <asm/cpu_has_feature.h>
		#include "nonstdio.h"
		#include "ansidecl.h"
		#include "ppc.h"
		#include <stdio.h>
		#include "sysdep.h"
		#include "dis-asm.h"
		#include "opcode/ppc.h"

		/* Print a PowerPC or POWER instruction. */
		/* This file provides several disassembler functions, all of which use
		the disassembler interface defined in dis-asm.h. Several functions
		are provided because this file handles disassembly for the PowerPC
		in both big and little endian mode and also for the POWER (RS/6000)
		chip. */

		static int print_insn_powerpc (bfd_vma, struct disassemble_info *, int, int);

		/* Determine which set of machines to disassemble for. PPC403/601 or
		BookE. For convenience, also disassemble instructions supported
		by the AltiVec vector unit. */

		static int
		powerpc_dialect (struct disassemble_info *info)
		{
		int dialect = PPC_OPCODE_PPC;

		if (BFD_DEFAULT_TARGET_SIZE == 64)
		dialect \|= PPC_OPCODE_64;

		if (info->disassembler_options
		&& strstr (info->disassembler_options, "booke") != NULL)
		dialect \|= PPC_OPCODE_BOOKE \| PPC_OPCODE_BOOKE64;
		else if ((info->mach == bfd_mach_ppc_e500)
		\|\| (info->disassembler_options
		&& strstr (info->disassembler_options, "e500") != NULL))
		dialect \|= (PPC_OPCODE_BOOKE
		\| PPC_OPCODE_SPE \| PPC_OPCODE_ISEL
		\| PPC_OPCODE_EFS \| PPC_OPCODE_BRLOCK
		\| PPC_OPCODE_PMR \| PPC_OPCODE_CACHELCK
		\| PPC_OPCODE_RFMCI);
		else if (info->disassembler_options
		&& strstr (info->disassembler_options, "efs") != NULL)
		dialect \|= PPC_OPCODE_EFS;
		else if (info->disassembler_options
		&& strstr (info->disassembler_options, "e300") != NULL)
		dialect \|= PPC_OPCODE_E300 \| PPC_OPCODE_CLASSIC \| PPC_OPCODE_COMMON;
		else if (info->disassembler_options
		&& strstr (info->disassembler_options, "440") != NULL)
		dialect \|= PPC_OPCODE_BOOKE \| PPC_OPCODE_32
		\| PPC_OPCODE_440 \| PPC_OPCODE_ISEL \| PPC_OPCODE_RFMCI;
		else
		dialect \|= (PPC_OPCODE_403 \| PPC_OPCODE_601 \| PPC_OPCODE_CLASSIC
		\| PPC_OPCODE_COMMON \| PPC_OPCODE_ALTIVEC);

		if (info->disassembler_options
		&& strstr (info->disassembler_options, "power4") != NULL)
		dialect \|= PPC_OPCODE_POWER4;

		if (info->disassembler_options
		&& strstr (info->disassembler_options, "power5") != NULL)
		dialect \|= PPC_OPCODE_POWER4 \| PPC_OPCODE_POWER5;

		if (info->disassembler_options
		&& strstr (info->disassembler_options, "cell") != NULL)
		dialect \|= PPC_OPCODE_POWER4 \| PPC_OPCODE_CELL \| PPC_OPCODE_ALTIVEC;

		if (info->disassembler_options
		&& strstr (info->disassembler_options, "power6") != NULL)
		dialect \|= PPC_OPCODE_POWER4 \| PPC_OPCODE_POWER5 \| PPC_OPCODE_POWER6 \| PPC_OPCODE_ALTIVEC;

		if (info->disassembler_options
		&& strstr (info->disassembler_options, "any") != NULL)
		dialect \|= PPC_OPCODE_ANY;

		if (info->disassembler_options)
		{
		if (strstr (info->disassembler_options, "32") != NULL)
		dialect &= ~PPC_OPCODE_64;
		else if (strstr (info->disassembler_options, "64") != NULL)
		dialect \|= PPC_OPCODE_64;
		}

		info->private_data = (char *) 0 + dialect;
		return dialect;
		}

		/* Print a big endian PowerPC instruction. */

		int
		print_insn_powerpc (unsigned long insn, unsigned long memaddr)
		print_insn_big_powerpc (bfd_vma memaddr, struct disassemble_info *info)
		{
		int dialect = (char ) info->private_data - (char ) 0;
		return print_insn_powerpc (memaddr, info, 1, dialect);
		}

		/* Print a little endian PowerPC instruction. */

		int
		print_insn_little_powerpc (bfd_vma memaddr, struct disassemble_info *info)
		{
		int dialect = (char ) info->private_data - (char ) 0;
		return print_insn_powerpc (memaddr, info, 0, dialect);
		}

		/* Print a POWER (RS/6000) instruction. */

		int
		print_insn_rs6000 (bfd_vma memaddr, struct disassemble_info *info)
		{
		return print_insn_powerpc (memaddr, info, 1, PPC_OPCODE_POWER);
		}

		/* Extract the operand value from the PowerPC or POWER instruction. */

		static long
		operand_value_powerpc (const struct powerpc_operand *operand,
		unsigned long insn, int dialect)
		{
		long value;
		int invalid;
		/* Extract the value from the instruction. */
		if (operand->extract)
		value = (*operand->extract) (insn, dialect, &invalid);
		else
		{
		value = (insn >> operand->shift) & operand->bitm;
		if ((operand->flags & PPC_OPERAND_SIGNED) != 0)
		{
		/* BITM is always some number of zeros followed by some
		number of ones, followed by some numer of zeros. */
		unsigned long top = operand->bitm;
		/* top & -top gives the rightmost 1 bit, so this
		fills in any trailing zeros. */
		top \|= (top & -top) - 1;
		top &= ~(top >> 1);
		value = (value ^ top) - top;
		}
		}

		return value;
		}

		/* Determine whether the optional operand(s) should be printed. */

		static int
		skip_optional_operands (const unsigned char *opindex,
		unsigned long insn, int dialect)
		{
		const struct powerpc_operand *operand;

		for (; *opindex != 0; opindex++)
		{
		operand = &powerpc_operands[*opindex];
		if ((operand->flags & PPC_OPERAND_NEXT) != 0
		\|\| ((operand->flags & PPC_OPERAND_OPTIONAL) != 0
		&& operand_value_powerpc (operand, insn, dialect) != 0))
		return 0;
		}

		return 1;
		}

		/* Print a PowerPC or POWER instruction. */

		static int
		print_insn_powerpc (bfd_vma memaddr,
		struct disassemble_info *info,
		int bigendian,
		int dialect)
		{
		bfd_byte buffer[4];
		int status;
		unsigned long insn;
		const struct powerpc_opcode *opcode;
		const struct powerpc_opcode *opcode_end;
		unsigned long op;
		int dialect;

		dialect = PPC_OPCODE_PPC \| PPC_OPCODE_CLASSIC \| PPC_OPCODE_COMMON
		\| PPC_OPCODE_64 \| PPC_OPCODE_POWER4 \| PPC_OPCODE_ALTIVEC;
		if (dialect == 0)
		dialect = powerpc_dialect (info);

		if (cpu_has_feature(CPU_FTRS_POWER5))
		dialect \|= PPC_OPCODE_POWER5;

		if (cpu_has_feature(CPU_FTRS_CELL))
		dialect \|= PPC_OPCODE_CELL \| PPC_OPCODE_ALTIVEC;
		status = (*info->read_memory_func) (memaddr, buffer, 4, info);
		if (status != 0)
		{
		(*info->memory_error_func) (status, memaddr, info);
		return -1;
		}

		if (cpu_has_feature(CPU_FTRS_POWER6))
		dialect \|= PPC_OPCODE_POWER5 \| PPC_OPCODE_POWER6 \| PPC_OPCODE_ALTIVEC;
		if (bigendian)
		insn = bfd_getb32 (buffer);
		else
		insn = bfd_getl32 (buffer);

		/* Get the major opcode of the instruction. */
		op = PPC_OP (insn);
		@@ -63,6 +222,7 @@ print_insn_powerpc (unsigned long insn, unsigned long memaddr)
		int invalid;
		int need_comma;
		int need_paren;
		int skip_optional;

		table_op = PPC_OP (opcode->opcode);
		if (op < table_op)
		@@ -88,13 +248,15 @@ print_insn_powerpc (unsigned long insn, unsigned long memaddr)
		continue;

		/* The instruction is valid. */
		printf("%s", opcode->name);
		if (opcode->operands[0] != 0)
		printf("\t");
		(*info->fprintf_func) (info->stream, "%-7s ", opcode->name);
		else
		(*info->fprintf_func) (info->stream, "%s", opcode->name);

		/* Now extract and print the operands. */
		need_comma = 0;
		need_paren = 0;
		skip_optional = -1;
		for (opindex = opcode->operands; *opindex != 0; opindex++)
		{
		long value;
		@@ -107,49 +269,44 @@ print_insn_powerpc (unsigned long insn, unsigned long memaddr)
		if ((operand->flags & PPC_OPERAND_FAKE) != 0)
		continue;

		/* Extract the value from the instruction. */
		if (operand->extract)
		value = (*operand->extract) (insn, dialect, &invalid);
		else
		/* If all of the optional operands have the value zero,
		then don't print any of them. */
		if ((operand->flags & PPC_OPERAND_OPTIONAL) != 0)
		{
		value = (insn >> operand->shift) & ((1 << operand->bits) - 1);
		if ((operand->flags & PPC_OPERAND_SIGNED) != 0
		&& (value & (1 << (operand->bits - 1))) != 0)
		value -= 1 << operand->bits;
		if (skip_optional < 0)
		skip_optional = skip_optional_operands (opindex, insn,
		dialect);
		if (skip_optional)
		continue;
		}

		/* If the operand is optional, and the value is zero, don't
		print anything. */
		if ((operand->flags & PPC_OPERAND_OPTIONAL) != 0
		&& (operand->flags & PPC_OPERAND_NEXT) == 0
		&& value == 0)
		continue;
		value = operand_value_powerpc (operand, insn, dialect);

		if (need_comma)
		{
		printf(",");
		(*info->fprintf_func) (info->stream, ",");
		need_comma = 0;
		}

		/* Print the operand as directed by the flags. */
		if ((operand->flags & PPC_OPERAND_GPR) != 0
		\|\| ((operand->flags & PPC_OPERAND_GPR_0) != 0 && value != 0))
		printf("r%ld", value);
		(*info->fprintf_func) (info->stream, "r%ld", value);
		else if ((operand->flags & PPC_OPERAND_FPR) != 0)
		printf("f%ld", value);
		(*info->fprintf_func) (info->stream, "f%ld", value);
		else if ((operand->flags & PPC_OPERAND_VR) != 0)
		printf("v%ld", value);
		(*info->fprintf_func) (info->stream, "v%ld", value);
		else if ((operand->flags & PPC_OPERAND_RELATIVE) != 0)
		print_address (memaddr + value);
		(*info->print_address_func) (memaddr + value, info);
		else if ((operand->flags & PPC_OPERAND_ABSOLUTE) != 0)
		print_address (value & 0xffffffff);
		(*info->print_address_func) ((bfd_vma) value & 0xffffffff, info);
		else if ((operand->flags & PPC_OPERAND_CR) == 0
		\|\| (dialect & PPC_OPCODE_PPC) == 0)
		printf("%ld", value);
		(*info->fprintf_func) (info->stream, "%ld", value);
		else
		{
		if (operand->bits == 3)
		printf("cr%ld", value);
		if (operand->bitm == 7)
		(*info->fprintf_func) (info->stream, "cr%ld", value);
		else
		{
		static const char *cbnames[4] = { "lt", "gt", "eq", "so" };
		@@ -158,15 +315,15 @@ print_insn_powerpc (unsigned long insn, unsigned long memaddr)

		cr = value >> 2;
		if (cr != 0)
		printf("4*cr%d+", cr);
		(info->fprintf_func) (info->stream, "4cr%d+", cr);
		cc = value & 3;
		printf("%s", cbnames[cc]);
		(*info->fprintf_func) (info->stream, "%s", cbnames[cc]);
		}
		}

		if (need_paren)
		{
		printf(")");
		(*info->fprintf_func) (info->stream, ")");
		need_paren = 0;
		}

		@@ -174,7 +331,7 @@ print_insn_powerpc (unsigned long insn, unsigned long memaddr)
		need_comma = 1;
		else
		{
		printf("(");
		(*info->fprintf_func) (info->stream, "(");
		need_paren = 1;
		}
		}
		@@ -190,7 +347,26 @@ print_insn_powerpc (unsigned long insn, unsigned long memaddr)
		}

		/* We could not find a match. */
		printf(".long 0x%lx", insn);
		(*info->fprintf_func) (info->stream, ".long 0x%lx", insn);

		return 4;
		}

		void
		print_ppc_disassembler_options (FILE *stream)
		{
		fprintf (stream, "\n\
		The following PPC specific disassembler options are supported for use with\n\
		the -M switch:\n");

		fprintf (stream, " booke\|booke32\|booke64 Disassemble the BookE instructions\n");
		fprintf (stream, " e300 Disassemble the e300 instructions\n");
		fprintf (stream, " e500\|e500x2 Disassemble the e500 instructions\n");
		fprintf (stream, " 440 Disassemble the 440 instructions\n");
		fprintf (stream, " efs Disassemble the EFS instructions\n");
		fprintf (stream, " power4 Disassemble the Power4 instructions\n");
		fprintf (stream, " power5 Disassemble the Power5 instructions\n");
		fprintf (stream, " power6 Disassemble the Power6 instructions\n");
		fprintf (stream, " 32 Do not disassemble 64-bit instructions\n");
		fprintf (stream, " 64 Allow disassembly of 64-bit instructions\n");
		}

arch/powerpc/xmon/ppc-opc.c

+235 −493

File changed.

Preview size limit exceeded, changes collapsed.

arch/powerpc/xmon/ppc.h

+33 −29

Original line number	Diff line number	Diff line
		/* ppc.h -- Header file for PowerPC opcode table
		Copyright 1994, 1995, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006
		Free Software Foundation, Inc.
		Copyright 1994, 1995, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006,
		2007 Free Software Foundation, Inc.
		Written by Ian Lance Taylor, Cygnus Support

		This file is part of GDB, GAS, and the GNU binutils.
		@@ -153,20 +153,21 @@ extern const int powerpc_num_opcodes;

		struct powerpc_operand
		{
		/* The number of bits in the operand. */
		int bits;
		/* A bitmask of bits in the operand. */
		unsigned int bitm;

		/* How far the operand is left shifted in the instruction. */
		/* How far the operand is left shifted in the instruction.
		-1 to indicate that BITM and SHIFT cannot be used to determine
		where the operand goes in the insn. */
		int shift;

		/* Insertion function. This is used by the assembler. To insert an
		operand value into an instruction, check this field.

		If it is NULL, execute
		i \|= (op & ((1 << o->bits) - 1)) << o->shift;
		i \|= (op & o->bitm) << o->shift;
		(i is the instruction which we are filling in, o is a pointer to
		this structure, and op is the opcode value; this assumes twos
		complement arithmetic).
		this structure, and op is the operand value).

		If this field is not NULL, then simply call it with the
		instruction and the operand value. It will return the new value
		@@ -182,12 +183,11 @@ struct powerpc_operand
		extract this operand type from an instruction, check this field.

		If it is NULL, compute
		op = ((i) >> o->shift) & ((1 << o->bits) - 1);
		if ((o->flags & PPC_OPERAND_SIGNED) != 0
		&& (op & (1 << (o->bits - 1))) != 0)
		op -= 1 << o->bits;
		op = (i >> o->shift) & o->bitm;
		if ((o->flags & PPC_OPERAND_SIGNED) != 0)
		sign_extend (op);
		(i is the instruction, o is a pointer to this structure, and op
		is the result; this assumes twos complement arithmetic).
		is the result).

		If this field is not NULL, then simply call it with the
		instruction value. It will return the value of the operand. If
		@@ -205,17 +205,18 @@ struct powerpc_operand
		the operands field of the powerpc_opcodes table. */

		extern const struct powerpc_operand powerpc_operands[];
		extern const unsigned int num_powerpc_operands;

		/* Values defined for the flags field of a struct powerpc_operand. */

		/* This operand takes signed values. */
		#define PPC_OPERAND_SIGNED (01)
		#define PPC_OPERAND_SIGNED (0x1)

		/* This operand takes signed values, but also accepts a full positive
		range of values when running in 32 bit mode. That is, if bits is
		16, it takes any value from -0x8000 to 0xffff. In 64 bit mode,
		this flag is ignored. */
		#define PPC_OPERAND_SIGNOPT (02)
		#define PPC_OPERAND_SIGNOPT (0x2)

		/* This operand does not actually exist in the assembler input. This
		is used to support extended mnemonics such as mr, for which two
		@@ -223,14 +224,14 @@ extern const struct powerpc_operand powerpc_operands[];
		insert function with any op value. The disassembler should call
		the extract function, ignore the return value, and check the value
		placed in the valid argument. */
		#define PPC_OPERAND_FAKE (04)
		#define PPC_OPERAND_FAKE (0x4)

		/* The next operand should be wrapped in parentheses rather than
		separated from this one by a comma. This is used for the load and
		store instructions which want their operands to look like
		reg,displacement(reg)
		*/
		#define PPC_OPERAND_PARENS (010)
		#define PPC_OPERAND_PARENS (0x8)

		/* This operand may use the symbolic names for the CR fields, which
		are
		@@ -239,26 +240,26 @@ extern const struct powerpc_operand powerpc_operands[];
		cr4 4 cr5 5 cr6 6 cr7 7
		These may be combined arithmetically, as in cr2*4+gt. These are
		only supported on the PowerPC, not the POWER. */
		#define PPC_OPERAND_CR (020)
		#define PPC_OPERAND_CR (0x10)

		/* This operand names a register. The disassembler uses this to print
		register names with a leading 'r'. */
		#define PPC_OPERAND_GPR (040)
		#define PPC_OPERAND_GPR (0x20)

		/* Like PPC_OPERAND_GPR, but don't print a leading 'r' for r0. */
		#define PPC_OPERAND_GPR_0 (0100)
		#define PPC_OPERAND_GPR_0 (0x40)

		/* This operand names a floating point register. The disassembler
		prints these with a leading 'f'. */
		#define PPC_OPERAND_FPR (0200)
		#define PPC_OPERAND_FPR (0x80)

		/* This operand is a relative branch displacement. The disassembler
		prints these symbolically if possible. */
		#define PPC_OPERAND_RELATIVE (0400)
		#define PPC_OPERAND_RELATIVE (0x100)

		/* This operand is an absolute branch address. The disassembler
		prints these symbolically if possible. */
		#define PPC_OPERAND_ABSOLUTE (01000)
		#define PPC_OPERAND_ABSOLUTE (0x200)

		/* This operand is optional, and is zero if omitted. This is used for
		example, in the optional BF field in the comparison instructions. The
		@@ -266,7 +267,7 @@ extern const struct powerpc_operand powerpc_operands[];
		and the number of operands remaining for the opcode, and decide
		whether this operand is present or not. The disassembler should
		print this operand out only if it is not zero. */
		#define PPC_OPERAND_OPTIONAL (02000)
		#define PPC_OPERAND_OPTIONAL (0x400)

		/* This flag is only used with PPC_OPERAND_OPTIONAL. If this operand
		is omitted, then for the next operand use this operand value plus
		@@ -274,24 +275,27 @@ extern const struct powerpc_operand powerpc_operands[];
		hack is needed because the Power rotate instructions can take
		either 4 or 5 operands. The disassembler should print this operand
		out regardless of the PPC_OPERAND_OPTIONAL field. */
		#define PPC_OPERAND_NEXT (04000)
		#define PPC_OPERAND_NEXT (0x800)

		/* This operand should be regarded as a negative number for the
		purposes of overflow checking (i.e., the normal most negative
		number is disallowed and one more than the normal most positive
		number is allowed). This flag will only be set for a signed
		operand. */
		#define PPC_OPERAND_NEGATIVE (010000)
		#define PPC_OPERAND_NEGATIVE (0x1000)

		/* This operand names a vector unit register. The disassembler
		prints these with a leading 'v'. */
		#define PPC_OPERAND_VR (020000)
		#define PPC_OPERAND_VR (0x2000)

		/* This operand is for the DS field in a DS form instruction. */
		#define PPC_OPERAND_DS (040000)
		#define PPC_OPERAND_DS (0x4000)

		/* This operand is for the DQ field in a DQ form instruction. */
		#define PPC_OPERAND_DQ (0100000)
		#define PPC_OPERAND_DQ (0x8000)

		/* Valid range of operand is 0..n rather than 0..n-1. */
		#define PPC_OPERAND_PLUS1 (0x10000)

		/* The POWER and PowerPC assemblers use a few macros. We keep them
		with the operands table for simplicity. The macro table is an

Admin message