Commit cc64520f authored by Bjorn Helgaas's avatar Bjorn Helgaas
Browse files

Merge branch 'lorenzo/pci/mediatek' 

  - implement Mediatek chained IRQ handling (Honghui Zhang)

  - fix vendor ID & class type for Mediatek MT7622 (Honghui Zhang)

* lorenzo/pci/mediatek:
  PCI: mediatek: Implement chained IRQ handling setup
  PCI: mediatek: Set up vendor ID and class type for MT7622

# Conflicts:
#	drivers/pci/host/Kconfig
parents 741f8e7e 42fe2f91

drivers/pci/host/Kconfig

+1 −0
Original line number Diff line number Diff line
@@ -193,6 +193,7 @@ config PCIE_MEDIATEK 
	bool "MediaTek PCIe controller"

	depends on ARCH_MEDIATEK || COMPILE_TEST

	depends on OF

	depends on PCI_MSI_IRQ_DOMAIN

	select PCIEPORTBUS

	help

	  Say Y here if you want to enable PCIe controller support on

drivers/pci/host/pcie-mediatek.c

+141 −93
Original line number Diff line number Diff line
@@ -11,8 +11,10 @@ 
#include <linux/delay.h>

#include <linux/iopoll.h>

#include <linux/irq.h>

#include <linux/irqchip/chained_irq.h>

#include <linux/irqdomain.h>

#include <linux/kernel.h>

#include <linux/msi.h>

#include <linux/of_address.h>

#include <linux/of_pci.h>

#include <linux/of_platform.h>
@@ -68,6 +70,10 @@ 


/* PCIe V2 per-port registers */

#define PCIE_MSI_VECTOR		0x0c0



#define PCIE_CONF_VEND_ID	0x100

#define PCIE_CONF_CLASS_ID	0x106



#define PCIE_INT_MASK		0x420

#define INTX_MASK		GENMASK(19, 16)

#define INTX_SHIFT		16
@@ -127,13 +133,13 @@ struct mtk_pcie_port; 


/**

 * struct mtk_pcie_soc - differentiate between host generations

 * @has_msi: whether this host supports MSI interrupts or not

 * @need_fix_class_id: whether this host's class ID needed to be fixed or not

 * @ops: pointer to configuration access functions

 * @startup: pointer to controller setting functions

 * @setup_irq: pointer to initialize IRQ functions

 */

struct mtk_pcie_soc {

	bool has_msi;

	bool need_fix_class_id;

	struct pci_ops *ops;

	int (*startup)(struct mtk_pcie_port *port);

	int (*setup_irq)(struct mtk_pcie_port *port, struct device_node *node);
@@ -157,7 +163,9 @@ struct mtk_pcie_soc { 
 * @lane: lane count

 * @slot: port slot

 * @irq_domain: legacy INTx IRQ domain

 * @inner_domain: inner IRQ domain

 * @msi_domain: MSI IRQ domain

 * @lock: protect the msi_irq_in_use bitmap

 * @msi_irq_in_use: bit map for assigned MSI IRQ

 */

struct mtk_pcie_port {
@@ -175,7 +183,9 @@ struct mtk_pcie_port { 
	u32 lane;

	u32 slot;

	struct irq_domain *irq_domain;

	struct irq_domain *inner_domain;

	struct irq_domain *msi_domain;

	struct mutex lock;

	DECLARE_BITMAP(msi_irq_in_use, MTK_MSI_IRQS_NUM);

};
@@ -377,6 +387,7 @@ static int mtk_pcie_startup_port_v2(struct mtk_pcie_port *port) 
{

	struct mtk_pcie *pcie = port->pcie;

	struct resource *mem = &pcie->mem;

	const struct mtk_pcie_soc *soc = port->pcie->soc;

	u32 val;

	size_t size;

	int err;
@@ -405,6 +416,15 @@ static int mtk_pcie_startup_port_v2(struct mtk_pcie_port *port) 
	       PCIE_MAC_SRSTB | PCIE_CRSTB;

	writel(val, port->base + PCIE_RST_CTRL);



	/* Set up vendor ID and class code */

	if (soc->need_fix_class_id) {

		val = PCI_VENDOR_ID_MEDIATEK;

		writew(val, port->base + PCIE_CONF_VEND_ID);



		val = PCI_CLASS_BRIDGE_HOST;

		writew(val, port->base + PCIE_CONF_CLASS_ID);

	}



	/* 100ms timeout value should be enough for Gen1/2 training */

	err = readl_poll_timeout(port->base + PCIE_LINK_STATUS_V2, val,

				 !!(val & PCIE_PORT_LINKUP_V2), 20,
@@ -432,102 +452,129 @@ static int mtk_pcie_startup_port_v2(struct mtk_pcie_port *port) 
	return 0;

}



static int mtk_pcie_msi_alloc(struct mtk_pcie_port *port)

static void mtk_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)

{

	int msi;

	struct mtk_pcie_port *port = irq_data_get_irq_chip_data(data);

	phys_addr_t addr;



	msi = find_first_zero_bit(port->msi_irq_in_use, MTK_MSI_IRQS_NUM);

	if (msi < MTK_MSI_IRQS_NUM)

		set_bit(msi, port->msi_irq_in_use);

	else

		return -ENOSPC;

	/* MT2712/MT7622 only support 32-bit MSI addresses */

	addr = virt_to_phys(port->base + PCIE_MSI_VECTOR);

	msg->address_hi = 0;

	msg->address_lo = lower_32_bits(addr);



	msg->data = data->hwirq;



	return msi;

	dev_dbg(port->pcie->dev, "msi#%d address_hi %#x address_lo %#x\n",

		(int)data->hwirq, msg->address_hi, msg->address_lo);

}



static void mtk_pcie_msi_free(struct mtk_pcie_port *port, unsigned long hwirq)

static int mtk_msi_set_affinity(struct irq_data *irq_data,

				const struct cpumask *mask, bool force)

{

	clear_bit(hwirq, port->msi_irq_in_use);

	 return -EINVAL;

}



static int mtk_pcie_msi_setup_irq(struct msi_controller *chip,

				  struct pci_dev *pdev, struct msi_desc *desc)

static void mtk_msi_ack_irq(struct irq_data *data)

{

	struct mtk_pcie_port *port;

	struct msi_msg msg;

	unsigned int irq;

	int hwirq;

	phys_addr_t msg_addr;

	struct mtk_pcie_port *port = irq_data_get_irq_chip_data(data);

	u32 hwirq = data->hwirq;



	port = mtk_pcie_find_port(pdev->bus, pdev->devfn);

	if (!port)

		return -EINVAL;

	writel(1 << hwirq, port->base + PCIE_IMSI_STATUS);

}



	hwirq = mtk_pcie_msi_alloc(port);

	if (hwirq < 0)

		return hwirq;

static struct irq_chip mtk_msi_bottom_irq_chip = {

	.name			= "MTK MSI",

	.irq_compose_msi_msg	= mtk_compose_msi_msg,

	.irq_set_affinity	= mtk_msi_set_affinity,

	.irq_ack		= mtk_msi_ack_irq,

};



	irq = irq_create_mapping(port->msi_domain, hwirq);

	if (!irq) {

		mtk_pcie_msi_free(port, hwirq);

		return -EINVAL;

	}

static int mtk_pcie_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,

				     unsigned int nr_irqs, void *args)

{

	struct mtk_pcie_port *port = domain->host_data;

	unsigned long bit;



	chip->dev = &pdev->dev;

	WARN_ON(nr_irqs != 1);

	mutex_lock(&port->lock);



	irq_set_msi_desc(irq, desc);

	bit = find_first_zero_bit(port->msi_irq_in_use, MTK_MSI_IRQS_NUM);

	if (bit >= MTK_MSI_IRQS_NUM) {

		mutex_unlock(&port->lock);

		return -ENOSPC;

	}



	/* MT2712/MT7622 only support 32-bit MSI addresses */

	msg_addr = virt_to_phys(port->base + PCIE_MSI_VECTOR);

	msg.address_hi = 0;

	msg.address_lo = lower_32_bits(msg_addr);

	msg.data = hwirq;

	__set_bit(bit, port->msi_irq_in_use);



	mutex_unlock(&port->lock);



	pci_write_msi_msg(irq, &msg);

	irq_domain_set_info(domain, virq, bit, &mtk_msi_bottom_irq_chip,

			    domain->host_data, handle_edge_irq,

			    NULL, NULL);



	return 0;

}



static void mtk_msi_teardown_irq(struct msi_controller *chip, unsigned int irq)

static void mtk_pcie_irq_domain_free(struct irq_domain *domain,

				     unsigned int virq, unsigned int nr_irqs)

{

	struct pci_dev *pdev = to_pci_dev(chip->dev);

	struct irq_data *d = irq_get_irq_data(irq);

	irq_hw_number_t hwirq = irqd_to_hwirq(d);

	struct mtk_pcie_port *port;

	struct irq_data *d = irq_domain_get_irq_data(domain, virq);

	struct mtk_pcie_port *port = irq_data_get_irq_chip_data(d);



	port = mtk_pcie_find_port(pdev->bus, pdev->devfn);

	if (!port)

		return;

	mutex_lock(&port->lock);



	if (!test_bit(d->hwirq, port->msi_irq_in_use))

		dev_err(port->pcie->dev, "trying to free unused MSI#%lu\n",

			d->hwirq);

	else

		__clear_bit(d->hwirq, port->msi_irq_in_use);



	mutex_unlock(&port->lock);



	irq_dispose_mapping(irq);

	mtk_pcie_msi_free(port, hwirq);

	irq_domain_free_irqs_parent(domain, virq, nr_irqs);

}



static struct msi_controller mtk_pcie_msi_chip = {

	.setup_irq = mtk_pcie_msi_setup_irq,

	.teardown_irq = mtk_msi_teardown_irq,

static const struct irq_domain_ops msi_domain_ops = {

	.alloc	= mtk_pcie_irq_domain_alloc,

	.free	= mtk_pcie_irq_domain_free,

};



static struct irq_chip mtk_msi_irq_chip = {

	.name		= "MTK PCIe MSI",

	.irq_enable = pci_msi_unmask_irq,

	.irq_disable = pci_msi_mask_irq,

	.irq_ack	= irq_chip_ack_parent,

	.irq_mask	= pci_msi_mask_irq,

	.irq_unmask	= pci_msi_unmask_irq,

};



static int mtk_pcie_msi_map(struct irq_domain *domain, unsigned int irq,

			    irq_hw_number_t hwirq)

static struct msi_domain_info mtk_msi_domain_info = {

	.flags	= (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |

		   MSI_FLAG_PCI_MSIX),

	.chip	= &mtk_msi_irq_chip,

};



static int mtk_pcie_allocate_msi_domains(struct mtk_pcie_port *port)

{

	irq_set_chip_and_handler(irq, &mtk_msi_irq_chip, handle_simple_irq);

	irq_set_chip_data(irq, domain->host_data);

	struct fwnode_handle *fwnode = of_node_to_fwnode(port->pcie->dev->of_node);



	return 0;

	mutex_init(&port->lock);



	port->inner_domain = irq_domain_create_linear(fwnode, MTK_MSI_IRQS_NUM,

						      &msi_domain_ops, port);

	if (!port->inner_domain) {

		dev_err(port->pcie->dev, "failed to create IRQ domain\n");

		return -ENOMEM;

	}



static const struct irq_domain_ops msi_domain_ops = {

	.map = mtk_pcie_msi_map,

};

	port->msi_domain = pci_msi_create_irq_domain(fwnode, &mtk_msi_domain_info,

						     port->inner_domain);

	if (!port->msi_domain) {

		dev_err(port->pcie->dev, "failed to create MSI domain\n");

		irq_domain_remove(port->inner_domain);

		return -ENOMEM;

	}



	return 0;

}



static void mtk_pcie_enable_msi(struct mtk_pcie_port *port)

{
@@ -561,6 +608,7 @@ static int mtk_pcie_init_irq_domain(struct mtk_pcie_port *port, 
{

	struct device *dev = port->pcie->dev;

	struct device_node *pcie_intc_node;

	int ret;



	/* Setup INTx */

	pcie_intc_node = of_get_next_child(node, NULL);
@@ -577,27 +625,28 @@ static int mtk_pcie_init_irq_domain(struct mtk_pcie_port *port, 
	}



	if (IS_ENABLED(CONFIG_PCI_MSI)) {

		port->msi_domain = irq_domain_add_linear(node, MTK_MSI_IRQS_NUM,

							 &msi_domain_ops,

							 &mtk_pcie_msi_chip);

		if (!port->msi_domain) {

			dev_err(dev, "failed to create MSI IRQ domain\n");

			return -ENODEV;

		}

		ret = mtk_pcie_allocate_msi_domains(port);

		if (ret)

			return ret;



		mtk_pcie_enable_msi(port);

	}



	return 0;

}



static irqreturn_t mtk_pcie_intr_handler(int irq, void *data)

static void mtk_pcie_intr_handler(struct irq_desc *desc)

{

	struct mtk_pcie_port *port = (struct mtk_pcie_port *)data;

	struct mtk_pcie_port *port = irq_desc_get_handler_data(desc);

	struct irq_chip *irqchip = irq_desc_get_chip(desc);

	unsigned long status;

	u32 virq;

	u32 bit = INTX_SHIFT;



	while ((status = readl(port->base + PCIE_INT_STATUS)) & INTX_MASK) {

	chained_irq_enter(irqchip, desc);



	status = readl(port->base + PCIE_INT_STATUS);

	if (status & INTX_MASK) {

		for_each_set_bit_from(bit, &status, PCI_NUM_INTX + INTX_SHIFT) {

			/* Clear the INTx */

			writel(1 << bit, port->base + PCIE_INT_STATUS);
@@ -608,14 +657,12 @@ static irqreturn_t mtk_pcie_intr_handler(int irq, void *data) 
	}



	if (IS_ENABLED(CONFIG_PCI_MSI)) {

		while ((status = readl(port->base + PCIE_INT_STATUS)) & MSI_STATUS) {

		if (status & MSI_STATUS){

			unsigned long imsi_status;



			while ((imsi_status = readl(port->base + PCIE_IMSI_STATUS))) {

				for_each_set_bit(bit, &imsi_status, MTK_MSI_IRQS_NUM) {

					/* Clear the MSI */

					writel(1 << bit, port->base + PCIE_IMSI_STATUS);

					virq = irq_find_mapping(port->msi_domain, bit);

					virq = irq_find_mapping(port->inner_domain, bit);

					generic_handle_irq(virq);

				}

			}
@@ -624,7 +671,9 @@ static irqreturn_t mtk_pcie_intr_handler(int irq, void *data) 
		}

	}



	return IRQ_HANDLED;

	chained_irq_exit(irqchip, desc);



	return;

}



static int mtk_pcie_setup_irq(struct mtk_pcie_port *port,
@@ -635,20 +684,15 @@ static int mtk_pcie_setup_irq(struct mtk_pcie_port *port, 
	struct platform_device *pdev = to_platform_device(dev);

	int err, irq;



	irq = platform_get_irq(pdev, port->slot);

	err = devm_request_irq(dev, irq, mtk_pcie_intr_handler,

			       IRQF_SHARED, "mtk-pcie", port);

	if (err) {

		dev_err(dev, "unable to request IRQ %d\n", irq);

		return err;

	}



	err = mtk_pcie_init_irq_domain(port, node);

	if (err) {

		dev_err(dev, "failed to init PCIe IRQ domain\n");

		return err;

	}



	irq = platform_get_irq(pdev, port->slot);

	irq_set_chained_handler_and_data(irq, mtk_pcie_intr_handler, port);



	return 0;

}
@@ -1082,8 +1126,6 @@ static int mtk_pcie_register_host(struct pci_host_bridge *host) 
	host->map_irq = of_irq_parse_and_map_pci;

	host->swizzle_irq = pci_common_swizzle;

	host->sysdata = pcie;

	if (IS_ENABLED(CONFIG_PCI_MSI) && pcie->soc->has_msi)

		host->msi = &mtk_pcie_msi_chip;



	err = pci_scan_root_bus_bridge(host);

	if (err < 0)
@@ -1144,8 +1186,14 @@ static const struct mtk_pcie_soc mtk_pcie_soc_v1 = { 
	.startup = mtk_pcie_startup_port,

};



static const struct mtk_pcie_soc mtk_pcie_soc_v2 = {

	.has_msi = true,

static const struct mtk_pcie_soc mtk_pcie_soc_mt2712 = {

	.ops = &mtk_pcie_ops_v2,

	.startup = mtk_pcie_startup_port_v2,

	.setup_irq = mtk_pcie_setup_irq,

};



static const struct mtk_pcie_soc mtk_pcie_soc_mt7622 = {

	.need_fix_class_id = true,

	.ops = &mtk_pcie_ops_v2,

	.startup = mtk_pcie_startup_port_v2,

	.setup_irq = mtk_pcie_setup_irq,
@@ -1154,8 +1202,8 @@ static const struct mtk_pcie_soc mtk_pcie_soc_v2 = { 
static const struct of_device_id mtk_pcie_ids[] = {

	{ .compatible = "mediatek,mt2701-pcie", .data = &mtk_pcie_soc_v1 },

	{ .compatible = "mediatek,mt7623-pcie", .data = &mtk_pcie_soc_v1 },

	{ .compatible = "mediatek,mt2712-pcie", .data = &mtk_pcie_soc_v2 },

	{ .compatible = "mediatek,mt7622-pcie", .data = &mtk_pcie_soc_v2 },

	{ .compatible = "mediatek,mt2712-pcie", .data = &mtk_pcie_soc_mt2712 },

	{ .compatible = "mediatek,mt7622-pcie", .data = &mtk_pcie_soc_mt7622 },

	{},

};

include/linux/pci_ids.h

+2 −0
Original line number Diff line number Diff line
@@ -2120,6 +2120,8 @@ 


#define PCI_VENDOR_ID_MYRICOM		0x14c1



#define PCI_VENDOR_ID_MEDIATEK		0x14c3



#define PCI_VENDOR_ID_TITAN		0x14D2

#define PCI_DEVICE_ID_TITAN_010L	0x8001

#define PCI_DEVICE_ID_TITAN_100L	0x8010

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